Merge pull request #47 from sjthales/cv32a6_contest_24_25

contest edition 24 25

Makefile

@@ -108,7 +108,7 @@ endif
 # target takes one of the following cva6 hardware configuration:
 # cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32, cv32a6_ima_sv32_fpga
 # Changing the default target to cv32a60x for Step1 verification
-target     ?= cv32a6_ima_sv32_fpga
+target     ?= cv32a6_im_contest
 ifndef TARGET_CFG
 	export TARGET_CFG = $(target)
 endif

README.md

@@ -10,7 +10,7 @@ $ git clone https://github.com/ThalesGroup/cva6-softcore-contest.git
 $ git submodule update --init --recursive
 ```
 
-Do not forget to check all the details of the contest in [Annonce RISC-V contest 2023-2024 v2.pdf](./Annonce%20RISC-V%20contest%202023-2024%20v2.pdf).
+Do not forget to check all the details of the contest in [Annonce RISC-V contest 2024-2025.pdf](./Annonce%20RISC-V%20contest%202024-2025.pdf).
 
 This repository contains the files needed for the 2021-2022 contest focusing on energy efficiency. The 2020-2021 contest focusing on the performance can be retrieved in this repository under the cv32a6_contest_2020 GitHub tag.
 
@@ -23,16 +23,16 @@ Other simulation tools and versions will receive no support from the organizatio
 
 ## Vitis/Vivado setting up
 For the contest, the CVA6 processor will be implemented on Zybo Z7-20 board from Digilent. This board integrates a Zynq 7000 FPGA from Xilinx. 
-To do so, **Vitis 2020.1** environment from Xilinx needs to be installed.
+To do so, **Vitis 2024.1** environment from Xilinx needs to be installed.
 
 Furthermore, Digilent provides board files for each development board.
 
 These files ease the creation of new projects with automated configuration of several complicated components such as Zynq Processing System and memory interfaces.
 
-All guidelines to install **vitis 2020.1** and **Zybo Z7-20** board files are explained in
+All guidelines to install **vitis 2024.1** and **Zybo Z7-20** board files are explained in
 https://reference.digilentinc.com/reference/programmable-logic/guides/installation.
 
-**Be careful about your linux distribution and the supported version of Vitis 2020.1 environment.**
+**Be careful about your linux distribution and the supported version of Vitis 2024.1 environment.**
 
 
 
@@ -82,6 +82,13 @@ Now, the hardware is ready and the hyperterminal is connected to the UART output
 
 ## Get started with software environment
 
+The executables of MNIST & CoreMark applications are already available in **sw/app**, but can be recompiled. 
+
+To get the CoreMark source files, apply the patch **coremark.patch**:
+```
+git apply coremark.patch
+```
+
 ### Building the docker image
 
 Install Docker on the workstation.
@@ -211,8 +218,8 @@ Expected  = 4
 Predicted = 4
 Result : 1/1
 credence: 82
-image env0003: 1731593 instructions
-image env0003: 2353693 cycles
+image env0003: 1753389 instructions
+image env0003: 2818904 cycles
 ```
 
 This result is obtained just after the FPGA bitstream loading.
@@ -251,8 +258,8 @@ Expected  = 4
 Predicted = 4
 Result : 1/1
 credence: 82
-image env0003: 1731593 instructions
-image env0003: 2316653 cycles
+image env0003: 1753389 instructions
+image env0003: 2721823 cycles
 ```
 
 CVA6 software environment is detailed into `sw/app` directory.
@@ -276,7 +283,7 @@ By default, synthesis is performed in batch mode, however it is possible to run
 ```
 $ make cva6_ooc CLK_PERIOD_NS=20 BATCH_MODE=0
 ```
-This command generates synthesis and place and route reports in **fpga/reports_cva6_ooc_synth** and **fpga/reports_cva6_ooc_impl**.
+This command generates synthesis and place and route reports in **corev_apu/fpga/reports_cva6_ooc_synth** and **corev_apu/fpga/reports_cva6_ooc_impl**.
 
 
 

core/frontend/btb.sv

@@ -82,7 +82,7 @@ module btb #(
     for (genvar i = 0; i < ariane_pkg::INSTR_PER_FETCH; i++) begin : gen_btb_output
       assign btb_ram_csel_prediction[i] = 1'b1;
       assign btb_ram_we_prediction[i] = 1'b0;
-      assign btb_ram_wdata_prediction = '0;
+      assign btb_ram_wdata_prediction[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]  = '0;
       assign btb_ram_addr_prediction[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = index;
       assign btb_prediction_o[i] = btb_ram_rdata_prediction[i*BRAM_WORD_BITS+:BRAM_WORD_BITS];
     end

core/include/cv32a6_im_contest_config_pkg.sv

@@ -0,0 +1,146 @@
+// Copyright 2021 Thales DIS design services SAS
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+// You may obtain a copy of the License at https://solderpad.org/licenses/
+//
+// Original Author: Jean-Roch COULON - Thales
+
+
+package cva6_config_pkg;
+
+  localparam CVA6ConfigXlen = 32;
+
+  localparam CVA6ConfigFpuEn = 0;
+  localparam CVA6ConfigF16En = 0;
+  localparam CVA6ConfigF16AltEn = 0;
+  localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigFVecEn = 0;
+
+  localparam CVA6ConfigCvxifEn = 0;
+  localparam CVA6ConfigCExtEn = 1;
+  //localparam CVA6ConfigZcbExtEn = 0;
+  localparam CVA6ConfigZcbExtEn = 1;
+  localparam CVA6ConfigAExtEn = 1;
+  //localparam CVA6ConfigBExtEn = 0;
+  localparam CVA6ConfigBExtEn = 1;
+  localparam CVA6ConfigVExtEn = 0;
+  //localparam CVA6ConfigZiCondExtEn = 0;
+  localparam CVA6ConfigZiCondExtEn = 1;
+
+  localparam CVA6ConfigAxiIdWidth = 4;
+  localparam CVA6ConfigAxiAddrWidth = 64;
+  localparam CVA6ConfigAxiDataWidth = 64;
+  localparam CVA6ConfigFetchUserEn = 0;
+  localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen;
+  localparam CVA6ConfigDataUserEn = 0;
+  localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen;
+
+  localparam CVA6ConfigIcacheByteSize = 8192;
+  localparam CVA6ConfigIcacheSetAssoc = 2;
+  localparam CVA6ConfigIcacheLineWidth = 128;
+  localparam CVA6ConfigDcacheByteSize = 8192;
+  localparam CVA6ConfigDcacheSetAssoc = 2;
+  localparam CVA6ConfigDcacheLineWidth = 128;
+
+  localparam CVA6ConfigDcacheIdWidth = 1;
+  localparam CVA6ConfigMemTidWidth = 2;
+
+  localparam CVA6ConfigWtDcacheWbufDepth = 2;
+
+  localparam CVA6ConfigNrCommitPorts = 1;
+  localparam CVA6ConfigNrScoreboardEntries = 4;
+
+  localparam CVA6ConfigFPGAEn = 1;
+
+  localparam CVA6ConfigNrLoadPipeRegs = 1;
+  //localparam CVA6ConfigNrLoadPipeRegs = 0;
+  localparam CVA6ConfigNrStorePipeRegs = 0;
+  localparam CVA6ConfigNrLoadBufEntries = 2;
+
+  localparam CVA6ConfigInstrTlbEntries = 2;
+  localparam CVA6ConfigDataTlbEntries = 2;
+
+  localparam CVA6ConfigRASDepth = 2;
+  localparam CVA6ConfigBTBEntries = 32;
+  localparam CVA6ConfigBHTEntries = 128;
+
+  localparam CVA6ConfigNrPMPEntries = 8;
+  //localparam CVA6ConfigNrPMPEntries = 0;
+
+  localparam CVA6ConfigPerfCounterEn = 1;
+
+  localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::WT;
+
+  localparam CVA6ConfigMmuPresent = 1;
+
+  localparam CVA6ConfigRvfiTrace = 1;
+
+  localparam config_pkg::cva6_cfg_t cva6_cfg = '{
+      NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
+      AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
+      AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
+      AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
+      AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
+      NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
+      FpuEn: bit'(CVA6ConfigFpuEn),
+      XF16: bit'(CVA6ConfigF16En),
+      XF16ALT: bit'(CVA6ConfigF16AltEn),
+      XF8: bit'(CVA6ConfigF8En),
+      RVA: bit'(CVA6ConfigAExtEn),
+      RVV: bit'(CVA6ConfigVExtEn),
+      RVC: bit'(CVA6ConfigCExtEn),
+      RVZCB: bit'(CVA6ConfigZcbExtEn),
+      XFVec: bit'(CVA6ConfigFVecEn),
+      CvxifEn: bit'(CVA6ConfigCvxifEn),
+      ZiCondExtEn: bit'(CVA6ConfigZiCondExtEn),
+      // Extended
+      RVF:
+      bit'(
+      0
+      ),
+      RVD: bit'(0),
+      FpPresent: bit'(0),
+      NSX: bit'(0),
+      FLen: unsigned'(0),
+      RVFVec: bit'(0),
+      XF16Vec: bit'(0),
+      XF16ALTVec: bit'(0),
+      XF8Vec: bit'(0),
+      NrRgprPorts: unsigned'(0),
+      NrWbPorts: unsigned'(0),
+      EnableAccelerator: bit'(0),
+      HaltAddress: 64'h800,
+      ExceptionAddress: 64'h808,
+      RASDepth: unsigned'(CVA6ConfigRASDepth),
+      BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      DmBaseAddress: 64'h0,
+      NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
+      NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
+      // idempotent region
+      NrNonIdempotentRules:
+      unsigned'(
+      2
+      ),
+      NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
+      NonIdempotentLength: 1024'({64'b0, 64'b0}),
+      NrExecuteRegionRules: unsigned'(3),
+      //                      DRAM,          Boot ROM,   Debug Module
+      ExecuteRegionAddrBase:
+      1024'(
+      {64'h8000_0000, 64'h1_0000, 64'h0}
+      ),
+      ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
+      // cached region
+      NrCachedRegionRules:
+      unsigned'(
+      1
+      ),
+      CachedRegionAddrBase: 1024'({64'h8000_0000}),
+      CachedRegionLength: 1024'({64'h40000000}),
+      MaxOutstandingStores: unsigned'(7)
+  };
+
+endpackage