Additional Updates for Documenter for System Verilog #609
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added functionality to pull 'include precompiler command into the documentor to build out a more detailed file. modified the documentor task function to not put all arguments on individual lines.
updated the description formatting for Tasks and Functions
Added green coloring to input, output, inout keywords for functions and tasks. bug found. if declaration is broken across multiple lines it does NOT like that.
Fixed port list of tasks and functions when broken across multiple lines.
missed semicolons and fixed bug where function or task with no params broke the output.
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could you add some tests? https://github.com/TerosTechnology/vscode-terosHDL/tree/dev/packages/colibri/tests/documenter |
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added handling of `include keyword to pull in HDL to build documentation.
fixed handling of arguments for Tasks and Functions.
made formatting changes for tasks/functions for readability.
should probably be rolled through the instantiations and always blocks in the documentro.