STM8 Low Density Devices
In the STM8 family there are STM8Sx03 "low density", STM8Sx05 "medium density", and STM8Sx07 "high density" devices which are presented in product lines:
- x=0: "Value Line"
- x=1: "Access Line"
- x=2: "Performance Line"
- x=9: "Application Specific Line"
The datasheets of the "Value Line" and "Access line" devices sometimes lists different features for the same "low density" or "medium density" chip. This page tries to list some findings about differences.
A comparison of datasheets between the "Value Line" STM8S003F3P6 and the "Access Line" STM8S103F3P6 suggests that it's basically the same silicon with a different spec (e.g. number of Flash write cycles), and with a specified EEPROM size (Value Line devices specify 128 bytes but tests show that up to 640 bytes may be available).
A new STM8S low-density errata sheet was published, the "STM8S001J3, STM8S003xx, STM8S103xx and STM8S903xx device limitations", which means that all these chips are at least "very similar".
In the STM8S001J3 datasheet there is a bit of information that didn't appear in the STM8S003 datasheet:
Note: The PA2, PB0, PB1, PB2, PB3, PB6, PB7, PC1, PC2, PC7, PD0, PD2, PD4, PD7, PE5 and PF4 GPIOs should be configured after device reset in output push-pull mode with output low-state to reduce the device’s consumption and to improve its EMC immunity. The GPIOs mentioned above are not connected to pins, and they are in input-floating mode after a device reset.
Only 32 pin devices provide the GPIOs mentioned in the note (e.g. LQFP32 STM8S003K3). The advice is thus also applicable to STM8S003F3 (i.e. PB1, PB2, PB3, PB6, PB7, PC1, PC2, PD0, PD7, PE5 and PF4).
The latest member of the STM8S00x "Value Line" is the STM8S001J3 in a SO8N package, which has about the same dimensions as the TSSOP20 but, due to the reduced pin count, is very easy to solder.
A note in the STM8S001J3 datasheet states that the STM8S001 is a member of the "low density family" and doesn't rely on a special silicon with more alternative pin functions:
Note: As several pins provide a connection to multiple GPIOs, the mode selection for any of those GPIOs impacts all the other GPIOs connected to the same pin. The user is responsible for the proper setting of the GPIO modes in order to avoid conflicts between GPIOs bonded to the same pin (including their alternate functions). For example, pull-up enabled on PD1 is also seen on PC6, PD3 and PD5. Push-pull configuration of PC3 is also seen on PC4 and PC5, etc.
This means that the SO8N package contains the same chip as a device with more pins (i.e. the STM8S903F3 in a TSSOP20 package). It should be possible to combine up to 4 GPIOs (pin 8) for push-pull of up to 80mA load within the specification (pin 8).
The following GPIOs/features are available:
| Pin | GPIO | Features |
|---|---|---|
| 1 | PA1 | OSC_IN |
| 1 | PD6 | UART1_RX, AIN6 |
| 5 | PA3 | TIM2_CH3, [SPI_NSS], [UART1_TX] |
| 5 | PB5 | I2C_SDA |
| 6 | PB4 | I2C_SCL, [ADC_ETR] |
| 7 | PC3 | TIM1_CH3, [TLI], [TIM1_CH1N] |
| 7 | PC4 | TIM1_CH4, CLK_CCO, AIN2, [TIM1_CH3] |
| 7 | PC5 | SPI_SCK, [TIM2_CH1] |
| 8 | PC6 | SPI_MOSI, [TIM1_CH1] |
| 8 | PD1 | SWIM |
| 8 | PD3 | TIM2_CH2, TIM2_CH2, ADC_ETR |
| 8 | PD5 | UART1_TX, AIN5 |
The Alternate Function options if the STM8S001J3 are identical with the STM8S903. Compared to the STM8S003 low density devices there are the following additional features:
- UART1_TX can be mapped to GPIO PA3
- Timer synchronization/chaining features (TIM5 and TIM6 instead of TIM2 and TIM4)
- AIN6 at GPIO PD6 (the STM8S903 has 6 analog inputs)
- AIN7 is connected to an internal bandgap reference
The timer and the bandgap reference features are undocumented. A test (7 ADC! ADC@ .) with a production sample results in 400 at 3.3V supply.