STM8 Low Density Devices
STM8 Low Density devices are among the cheapest micro-controllers available that are powerful enough to host an interactive programming environment. They can be divided in Standard (S) and Low Power (L) devices, and both families have at least two major variants.
Some industrial STM8S devices appear to be rebranded automotive STM8AF devices, and there are some hidden "application specific" features worth exploring.
STM8S "low density" devices can be divided in different variants, industrial (standard) and automotive. One devices that shares features with an automotive variant (the STM8S903) is marketed as a "Application Specific Line" device.
It's noteworthy that while peripherals of "low density" devices often have the same features as "medium" and "high density" devices the register addresses are sometimes different. This means that care must be tasken when writing device independent code. The address STM8S.efr contains notes about common and device specific peripheral register addresses.
Comparing features (i.e. datasheets and tests) suggests the following picture:
| Base | Similar products |
|---|---|
| STM8S103 | STM8S003, STM8AF6223 |
| STM8AF6226 | STM8AF6223A, STM8S903, , STM8S001J3M3 |
The STM8S Low-Density errata sheet makes no difference between "STM8S001J3, STM8S003xx, STM8S103xx and STM8S903xx device limitations", which means that all these chips are at least "very similar".
Note that the GPIO-pin assignment the STM8AF6223 (TSSOP20 package) is like STM8S103F3P6 and similar to STM8S903F3P6. STM8AF6226 in a 32 pin is like the STM8S903K3 but the STM8AF6223A (likely the same chip in a 20 pin package) has a different pin assignment compared with the STM8S903F3P6.
Both low density device types have a very similar set of peripherals but the STM8AF6226 "family" is more versatile:
- internal ADC channel with bandgap reference
- one more ADC input available
- cascadable timers (like STM8S Medium Density)
- UART GPIO pins reconfigurable from PD5-PD6 to PA3/PF4
This means that the STM8S103 features are more or less a subset of those of the STM8AF6226, so most applications written for the first device should work on the second.
This similarity between the STM8S103 and the STM8AF6223 suggests that the UART in both devices is a UART4 (LINUART) and not UART1 like documented in the STM8S103 datasheet. Also the STM8AF6223 datasheet specifies cascadable timers (TIM5, TIM6 instead of TIM2 and TIM4). Only if it's true that the STM8S103 can't perform "LIN Slave Mode" (e.g. baud rate synchronization), and doesn't have the "cascading timer" feature, then there are 3 types of STM8S Low Density devices. This remains to be tested.
STM8S103 is marketed as a commercial general purpose (i.e. not automotive) STM8S "low density" device.
A comparison of datasheets between the "Value Line" STM8S003F3P6 and the "Access Line" STM8S103F3P6 suggests that it's the same silicon with a different specification (e.g. number of Flash write cycles), and with a different specified EEPROM size (Value Line devices specify 128 bytes but tests show that up to the same amount as in the higher rated devices may be available).
Likewise, it's possible that the true Flash size of the STM8S103F2P6 is 8K instead of the specified 4K, as it's the case for all of the STM8S Medium Density devices tested so far by the author, e.g., an STM8S105K4T6C has 16K Flash specified but it appears to have 32K. In practice these devices are rare.
In the STM8S001J3 datasheet there is a bit of information that's not in the STM8S003 datasheet:
Note: The PA2, PB0, PB1, PB2, PB3, PB6, PB7, PC1, PC2, PC7, PD0, PD2, PD4, PD7, PE5 and PF4 GPIOs should be configured after device reset in output push-pull mode with output low-state to reduce the device’s consumption and to improve its EMC immunity. The GPIOs mentioned above are not connected to pins, and they are in input-floating mode after a device reset.
Only 32 pin devices provide the GPIOs mentioned in the note (e.g. LQFP32 STM8S003K3). The advice is thus also applicable to STM8S003F3 (i.e. PB1, PB2, PB3, PB6, PB7, PC1, PC2, PD0, PD7, PE5 and PF4).
The latest member of the STM8S00x "Value Line" is the STM8S001J3 in a SO8N package, which has about the same dimensions as the TSSOP20 but, due to the reduced pin count, hand-soldering is very easy.
A note in the STM8S001J3 datasheet states that the STM8S001 is a member of the "low density family", and it's not a special "stripped down" silicon with (curiously) more alternative pin functions:
Note: As several pins provide a connection to multiple GPIOs, the mode selection for any of those GPIOs impacts all the other GPIOs connected to the same pin. The user is responsible for the proper setting of the GPIO modes in order to avoid conflicts between GPIOs bonded to the same pin (including their alternate functions). For example, pull-up enabled on PD1 is also seen on PC6, PD3 and PD5. Push-pull configuration of PC3 is also seen on PC4 and PC5, etc.
This means that the SO8N package contains the same chip as a device with more pins (i.e. the "Application Specific Line" device STM8S903F3 in a TSSOP20 package). It should be possible to combine up to 4 GPIOs (pin 8) for push-pull of up to 80mA load within the specification (pin 8).
The following GPIOs/features are available:
| Pin | GPIO | Features |
|---|---|---|
| 1 | PA1 | OSC_IN |
| 1 | PD6 | UART1_RX, AIN6 |
| 5 | PA3 | TIM2_CH3, [SPI_NSS], [UART1_TX] |
| 5 | PB5 | I2C_SDA |
| 6 | PB4 | I2C_SCL, [ADC_ETR] |
| 7 | PC3 | TIM1_CH3, [TLI], [TIM1_CH1N] |
| 7 | PC4 | TIM1_CH4, CLK_CCO, AIN2, [TIM1_CH3] |
| 7 | PC5 | SPI_SCK, [TIM2_CH1] |
| 8 | PC6 | SPI_MOSI, [TIM1_CH1] |
| 8 | PD1 | SWIM |
| 8 | PD3 | TIM2_CH2, TIM2_CH2, ADC_ETR |
| 8 | PD5 | UART1_TX, AIN5 |
The Alternate Function options if the STM8S001J3 are identical with those of the STM8S903. This means that compared with STM8S003 Low Density devices there are additional features:
- UART1_TX can be mapped to GPIO PA3
- Timer synchronization/chaining features (TIM5 and TIM6 instead of TIM2 and TIM4)
- AIN6 at GPIO PD6 (the STM8S903 has 6 analog inputs)
- AIN7 is connected to an internal bandgap reference
The timer and the bandgap reference features are undocumented but a test (e.g. querying the ADC7 with 7 ADC! ADC@ . in STM8 eForth) results in 400 at roughly 3.3V supply, which is consistent with the specs (the STM8S903 datasheet specifies the reference as 1.19 to 1.25V).
When comparing the UART features in Table 52 of the STM8S Reference Manual RM0016 it's a curious fact that "NA" doesn't mean "Not Available" but "Not Applicable". Since it's hard to see that there are should be two styles of UART1 (one in STM8S903 and STM8S001 devices, the other in STM8S103), it's likely that the name "UART1" in the STM8S903 and STM8S001 datasheets is misleading, and that these devices have a "UART4" ("LINUART") with full LIN features like the STM8AF6226. This remains to be tested.
Whoever assigned the GPIOs to SO8 pins must have a particular set of requirements. A final assessment if the solution we now see should also look at constraints, like the position of bond pads on the die that may have caused some "non features" and restrictions of usability:
- when UART1_TX is mapped to GPIO PA3, UART1_RX is hidden (mapped to GPIO PF4, not connected)
- high risk of lock-out when using a full-duplex UART (why share PD1 pin with PD5, not PD6?)
- no SPI MISO - the SPI is limited to the rarely used half-duplex mode
As stated before, it's much safer use the UART in half-duplex mode (since PD1/SWIM is available whenever the UART isn't sending). It's safer still to use PA3 instead PD5.
Here is how to set the option bytes for the alternative mapping:
echo "00 00 ff 03 fc 00 ff 00 ff 00 ff" | xxd -r -p > stm8s001_uart_pa3.bin
stm8flash -c stlinkv2 -p stm8s103f3 -s opt -w stm8s001_uart_pa3.bin
In STM8 eForth, it's possible to do that in an on-line session:
#require OPT!
\res MCU: STM8S103
\res export OPT2
3 OPT2 OPT!
RESETSwitching back can be done by loading the code above and typing 0 OPT2 OPT!.
STM8 Low Density devices consist of two distinct families:
- STM8L101, including STM8L001J3M3 (SO8)
- STM8L05x, including STM8L050J3M3 (SO8)
An STM8L101-like Low Density device has 1.5K RAM (instead of only 1K ) but it lacks RTC and ADC. The hallmark of this chip is a low complexity (even compared with STM8S).
More information is in the README of the STM8L101F3 STM8 eForth configuration.
Peripherals are superior to those in STM8S (e.g. RTC, 12 Bit ADC, Vcap not required), but they also show important changes with respect to the standard family (GPIO interrupts) and it's absurdly difficult to learn about differences and commonalities. One should think that it's easy for a company like ST to provide a synopsis to make the migration of applications easier, but it's likely that the management went the way of the automotive industry (i.e. they replicated the STM8S organization, and the STM8L tribe doesn't even know the STM8S docs).
More information is in the README of the STM8L051F3 STM8 eForth configuration.