An academic project for CE409 in University of Information and Technology, Vietnam. In this project, we design a Router16x16 by Verilog and verify it by SystemVerilog
Note: + Download Vivado 2023.2 + Read the Lab_Guide and Lab_Report carefully + If you have any idea for a change, please contact us by [email protected]
Since it is an academic project and we are new to SystemVerilog, we also want to have more opinions to gain experience and knowledge to make a better version in the future.