Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

How can I get a VGA signal in addition to HDMI? #67

Open
jmio opened this issue Oct 17, 2021 · 8 comments
Open

How can I get a VGA signal in addition to HDMI? #67

jmio opened this issue Oct 17, 2021 · 8 comments

Comments

@jmio
Copy link

jmio commented Oct 17, 2021

Hi,

I am continuing to learn SaxonSoc's Minimal sample.
I've got VGA (HDMI) from SDRAM working.
I want to output to HDMI, but also externally extract the VGA signal for LCD.

I think SaxonSoC automatically creates the inputs and outputs with InOutWrapper.
In this case, how should I describe it?

ICESugarProMinimal.scala

@Dolu1990
Copy link
Member

Hi,

I guess below : https://github.com/jmio/SaxonSoc/blob/vga_dma/hardware/scala/saxon/board/muselab/ICESugerPro/ICESugarProMinimal.scala#L170

val vgaPhy = vga.withRegisterPhy(withColorEn = false)

should be good ?

@jmio
Copy link
Author

jmio commented Oct 18, 2021

Oh! It worked. Thank you very much(^^)

I've read up on withRegisterPhy(), but I'm still not sure how it works.
I want to take the internal signal (VgaCtrl.io.xxxx) out to create a text screen overlay.

I know it's not a good way to do it, but I can't do it in Spinal yet, so I want to do it in Verilog(^^;

In this case, how can I get the signal from BmbVgaCtrl.io and then bring it to the top level?

@Dolu1990
Copy link
Member

ahhh
Then

val vgaBus = Handle(vga.output.toIo) 

should be fine ?

@jmio
Copy link
Author

jmio commented Oct 19, 2021

It worked like magic !

I would like to know what kind of rules make it work this way.
Is there any code that can help me understand it?

@Dolu1990
Copy link
Member

I would like to know what kind of rules make it work this way.

So, SaxonSoc is kind of a paradigme on the top of SpinalHDL, it use the fiber stuff to specify things in a "distributed" manner :
https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/fiber.html

Basicaly, Handle{ ... } fork a new thread to execute the given chunk of code, which can do active blocking when one of the thing it try to access isn't generated yet.

Then the "toIo" is a regular SpinalHDL thing to propagate io from a child component to the parent component.

Is there any code that can help me understand it?

Hmmm, the whole SaxonSoc stuff ^^
I mean, in general, be sure to have a proper IDE to explore the code, it reaaaaly help, me i'm on intellij.

@jmio
Copy link
Author

jmio commented Oct 19, 2021

Thank you for your answer.

I managed to learn "toIo" (^^;
I'll also try Intellij IDE.

I pull out the VgaCtrl.vga.ctrl.io.frameStart using "toIo", saw the following error

[error] HIERARCHY VIOLATION, (toplevel/system_vga_logic/vga_ctrl/io_frameStart : out Bool) can't be used in toplevel at
[error]     saxon.board.muselab.ICESugarPro.ICESugarProMinimal$$anonfun$6$$anon$5$$anonfun$8.apply(ICESugarProMinimal.scala:223)
[error]     saxon.board.muselab.ICESugarPro.ICESugarProMinimal$$anonfun$6$$anon$5$$anonfun$8.apply(ICESugarProMinimal.scala:223)
[error]     spinal.sim.JvmThread.run(SimManager.scala:51)

I was able to get "frameStart" out, but...
So, I ended up copying the definitions of the three classes in their entirety.

(jmio@35020f5#diff-b9270f6802cfabf0bd12a5a10a5754fa879eb61bc5551fcdd28310c206e47331)

I guess I need to learn Scala properly (^^;

@Dolu1990
Copy link
Member

Ahhh if you go more than one level deep into the hearchy, you have to do a :

VgaCtrl.vga.ctrl.io.frameStart.pull().toIo

That should work, as long that everything pulled is just for read (not for write) ^^

jmio added a commit to jmio/SaxonSoc that referenced this issue Oct 21, 2021
@jmio
Copy link
Author

jmio commented Oct 21, 2021

pull().toIo is handy (^^)

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

2 participants