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L2 cache writeback Counter of specific core #61

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SoCScholar opened this issue Nov 4, 2023 · 5 comments
Open

L2 cache writeback Counter of specific core #61

SoCScholar opened this issue Nov 4, 2023 · 5 comments

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@SoCScholar
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SoCScholar commented Nov 4, 2023

Hi

As 1 miss => 1 refill (for the current config), i am wondering how to measure L2 cache Write Back(WB) of specific cpu core?

i am wondering how to update here ?

https://github.com/SpinalHDL/NaxRiscv/blob/throttle_l2/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala#L120
 // Tweek the toplevel a bit
 class SocDemoSim(cpuCount : Int) extends SocDemo(cpuCount, withL2 = withL2, asic = asic){
   setDefinitionName("SocDemo")
   // You can for instance override cache parameters of the CPU caches like that :
   naxes.flatMap(_.plugins).foreach{
     case p : FetchCachePlugin => //p.cacheSize = 2048
     case p : DataCachePlugin =>  //p.cacheSize = 2048
     case _ =>
   }

   // l2.cache.parameter.cacheBytes = 4096

   // Here we add a scope peripheral, which can count the number of cycle that a given signal is high
   // See ext/NaxSoftware/baremetal/socdemo for software usages
   val scope = new ScopeFiber(){
     up at 0x04000000 of peripheral.bus
     lock.retain()

     val filler = Fiber build new Area {
       if (withL2) {
         val l2c = l2.cache.logic.cache
         add(l2c.events.acquire.hit, 0xF00) //acquire is used by data cache
         add(l2c.events.acquire.miss, 0xF04)
         add(l2c.events.getPut.hit, 0xF20) //getPut is used by instruction cache refill and DMA
         add(l2c.events.getPut.miss, 0xF24)
       }
       for ((nax, i) <- naxes.zipWithIndex) nax.plugins.foreach {
         case p: FetchCachePlugin => add(p.logic.refill.fire, i * 0x80 + 0x000)
         case p: DataCachePlugin => {
           add(p.logic.cache.refill.push.fire, i * 0x80 + 0x010)
           add(p.logic.cache.writeback.push.fire, i * 0x80 + 0x014)
           if (withL2) {
             val l2c = l2.cache.logic.cache
             l2c.rework{
               //For each core, generate a L2 d$ miss probe
               val masterSpec = l2c.p.unp.m.masters.find(_.name == p).get
               val masterHit = masterSpec.sourceHit(l2c.ctrl.processStage(l2c.CTRL_CMD).source)
               add((masterHit && l2c.events.acquire.miss).setCompositeName(l2c.events.acquire.miss, s"nax_$i"), i * 0x80 + 0x40)
             }
           }
         }
         case _ =>
       }
       lock.release()
     }
   }
   
   ```
@SoCScholar SoCScholar changed the title L2 cache writeback L2 cache writeback Counter of specific core Nov 4, 2023
@Dolu1990
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Dolu1990 commented Nov 6, 2023

Hi,

It is kinda complicated, as the writeback decision of the previous line doesn't occure in a single point :

  • If the replaced line is dirty => do it
  • If the replaced line is clean, but has a owner with "unique" permission => the result of the probing may trigger the writeback in the future as a EVICT (preCtrl.IS_EVICT)

@SoCScholar
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SoCScholar commented Nov 6, 2023

doesn't occur in a single point

I guess we might need to write different if else statement

add((masterHit && l2c.events.acquire.miss).setCompositeName(l2c.events.acquire.miss, s"nax_$i"), i * 0x80 + 0x40)

I wonder Why + 0x40 for data cache miss?

https://github.com/SpinalHDL/NaxRiscv/blob/throttle_l2/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala#L120


  if (withL2) {
            val l2c = l2.cache.logic.cache
            l2c.rework{
              //For each core, generate a L2 d$ miss probe
              val masterSpec = l2c.p.unp.m.masters.find(_.name == p).get
              val masterHit = masterSpec.sourceHit(l2c.ctrl.processStage(l2c.CTRL_CMD).source)
              add((masterHit && l2c.events.acquire.miss).setCompositeName(l2c.events.acquire.miss, s"nax_$i"), i * 0x80 + 0x40)
              
              //This block will estimate the WB {

                         {

              add((masterHit && l2c.events.acquire.miss).setCompositeName(l2c.events.acquire.miss, s"nax_$i"), i * 0x80 + 4*0x14) // 4 is number of way and 0x014 is offset use in  L1  cache.writeback.push.fire ( WB)                
                     
                        when(preCtrl.IS_EVICT){
                                                              askWriteBackend := True
                                                              toWriteBackend.evict := True
                                                              toWriteBackend.toDownA := True
                                                              toWriteBackend.size := log2Up(blockSize)
    }                                                                                                                                                
            

                }
            
            
            }
            }
            }
             

@Dolu1990
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I wonder Why + 0x40 for data cache miss?

Why not, to make some space, could be more, could be less

@SoCScholar
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SoCScholar commented Nov 10, 2023

Why not, to make some space, could be more, could be less

Is it for the L2 cache? As L2 is an inclusive cache, which has a copy of L1 data

@Dolu1990
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That to leave some space for hart specific non l2 probes, ex :
add(p.logic.cache.refill.push.fire, i * 0x80 + 0x010)
add(p.logic.cache.writeback.push.fire, i * 0x80 + 0x014)

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