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L2 cache writeback Counter of specific core #61
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Hi, It is kinda complicated, as the writeback decision of the previous line doesn't occure in a single point :
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I guess we might need to write different if else statement
I wonder Why + 0x40 for data cache miss?
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Why not, to make some space, could be more, could be less |
Is it for the L2 cache? As L2 is an inclusive cache, which has a copy of L1 data |
That to leave some space for hart specific non l2 probes, ex : |
Hi
As 1 miss => 1 refill (for the current config), i am wondering how to measure L2 cache Write Back(WB) of specific cpu core?
i am wondering how to update here ?
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