Create branch for backward compatibility of the MIO1.04 board

basil/HL/agilent_33250a.yaml

@@ -177,7 +177,7 @@ set_system_lock: SYSTem:RWLock
 ######
 # PLL commands
 ######
-set_pll_phase: PHASe #{Angle|MINimum|MAXimum}
+set_pll_phase: PHASe #{<:LQNHO>|MINimum|MAXimum}
 get_pll_phase: PHASe? #[MINimum|MAXimum]
 set_pll_reference: PHASe:REFerence
 set_pll_phase_error_state: PHASe:UNLock:ERRor:STATe #{OFF|ON}

basil/HL/fadc_rx.py

@@ -22,7 +22,10 @@ class fadc_rx(RegisterHardwareLayer):
                   'SINGLE_DATA': {'descr': {'addr': 2, 'size': 1, 'offset': 2}},
                   'SAMPLE_DLY': {'descr': {'addr': 7, 'size': 8}},
                   'COUNT': {'descr': {'addr': 3, 'size': 24}},
-                  'COUNT_LOST': {'descr': {'addr': 8, 'size': 8, 'properties': ['ro']}}}
+                  'COUNT_LOST': {'descr': {'addr': 8, 'size': 8, 'properties': ['ro']}},
+                  'CONF_TRIGGER_THRESHOLD' : {'descr':{'addr' : 9, 'size' : 8}},
+                  'CONF_SET_TRIGGER_THRESHOLD' : {'descr':{'addr' : 10, 'size' : 16}},
+                  'FEEDBACK_THRESHOLD_TRIGGERED' : {'descr':{'addr' : 12, 'size' : 8, 'properties' : ['ro']}}}
 
     _require_version = "==1"
 
@@ -79,3 +82,21 @@ def is_ready(self):
 
     def get_done(self):
         return self.is_ready
+
+    def set_threshold_trigger(self, mode):
+        self.CONF_TRIGGER_THRESHOLD = mode
+        # MODE 1: Check if value is smaller than threshold
+        # MODE 2: Check if value exceeds threshold
+        # MODE 3: Check if value changes more than threshold
+
+    def get_threshold_trigger_mode(self):
+        return self.CONF_TRIGGER_THRESHOLD
+
+    def set_threshold_trigger_value(self, val):
+        self.CONF_SET_TRIGGER_THRESHOLD = val
+
+    def get_threshold_trigger_value(self):
+        return self.CONF_SET_TRIGGER_THRESHOLD 
+
+    def get_threshold_trigger_feedback(self):
+        return self.FEEDBACK_THRESHOLD_TRIGGERED

basil/HL/seq_gen.py

@@ -18,15 +18,14 @@ class seq_gen(RegisterHardwareLayer):
                   'START': {'descr': {'addr': 1, 'size': 8, 'properties': ['writeonly']}},
                   'EN_EXT_START': {'descr': {'addr': 2, 'size': 1}},
                   'CLK_DIV': {'descr': {'addr': 3, 'size': 8}},
-                  'SIZE': {'descr': {'addr': 4, 'size': 32}},
-                  'WAIT': {'descr': {'addr': 8, 'size': 32}},
-                  'REPEAT': {'descr': {'addr': 12, 'size': 32}},
-                  'REPEAT_START': {'descr': {'addr': 16, 'size': 32}},
-                  'NESTED_START': {'descr': {'addr': 20, 'size': 32}},
-                  'NESTED_STOP': {'descr': {'addr': 24, 'size': 32}},
-                  'NESTED_REPEAT': {'descr': {'addr': 28, 'size': 32}},
-                  'MEM_BYTES': {'descr': {'addr': 32, 'size': 32, 'properties': ['ro']}},
-                  }
+                  'SIZE': {'descr': {'addr': 4, 'size': 16}},
+                  'WAIT': {'descr': {'addr': 6, 'size': 16}},
+                  'REPEAT': {'descr': {'addr': 8, 'size': 16}},
+                  'REPEAT_START': {'descr': {'addr': 10, 'size': 16}},
+                  'NESTED_START': {'descr': {'addr': 12, 'size': 16}},
+                  'NESTED_STOP': {'descr': {'addr': 14, 'size': 16}},
+                  'NESTED_REPEAT': {'descr': {'addr': 16, 'size': 16}},
+                  'MEM_BYTES': {'descr': {'addr': 18, 'size': 16, 'properties': ['ro']}},}
     _require_version = "==3"
 
     def __init__(self, intf, conf):

basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v

@@ -32,7 +32,9 @@ module gpac_adc_rx #(
     input wire           BUS_RD,
     input wire           BUS_WR,
 
-    output wire LOST_ERROR
+    output wire LOST_ERROR,
+	 output wire [0:1] status_LED
+
 );
 
 wire IP_RD, IP_WR;
@@ -79,7 +81,8 @@ gpac_adc_rx_core #(
     .FIFO_READ(FIFO_READ),
     .FIFO_EMPTY(FIFO_EMPTY),
     .FIFO_DATA(FIFO_DATA),
-    .LOST_ERROR(LOST_ERROR)
+    .LOST_ERROR(LOST_ERROR),
+	 .status_LED(status_LED)
 );
 
 

basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v

@@ -30,7 +30,8 @@ module gpac_adc_rx_core #(
     input wire BUS_WR,
     input wire BUS_RD,
 
-    output wire LOST_ERROR
+    output wire LOST_ERROR,
+	 output wire status_LED
 );
 
 localparam VERSION = 1;
@@ -41,6 +42,8 @@ localparam VERSION = 1;
 //TODO:
 // - external trigger /rising falling
 
+
+
 wire SOFT_RST;
 assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
 
@@ -60,6 +63,10 @@ always @(posedge BUS_CLK) begin
         status_regs[6] <= 1;
         status_regs[7] <= 0;
         status_regs[8] <= 0;
+		status_regs[9] <= 0;
+		status_regs[10] <= 0;
+		status_regs[11] <= 0;
+		status_regs[12] <= 0;
     end
     else if(BUS_WR && BUS_ADD < 16)
         status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
@@ -74,6 +81,7 @@ assign CONF_START_WITH_SYNC = status_regs[2][0];
 wire CONF_EN_EX_TRIGGER;
 assign CONF_EN_EX_TRIGGER = status_regs[2][1];
 
+
 wire CONF_SINGLE_DATA;
 assign CONF_SINGLE_DATA = status_regs[2][2];
 
@@ -91,6 +99,14 @@ reg CONF_DONE;
 wire [7:0] BUS_STATUS_OUT;
 assign BUS_STATUS_OUT = status_regs[BUS_ADD[3:0]];
 
+
+// Triggering on threshold condition registers
+wire [7:0] CONF_TRIGGER_THRESHOLD = status_regs[9]; // Enable threshold triggering
+wire [13:0] CONF_SET_TRIGGER_THRESHOLD = {status_regs[11][5:0], status_regs[10]}; // set the value for the threshold (depends on mode)
+reg [7:0] FEEDBACK_THRESHOLD_TRIGGERED; // A statusregister that gives basil a feedback, that it found an event
+reg [7:0] ADC_THRESHOLD; // The register that will hold the trigger information
+reg [13:0] ADC_IN_DLY_BUF; // Stores the most recent buf num
+
 always @(posedge BUS_CLK) begin
     if(BUS_RD) begin
         if(BUS_ADD == 0)
@@ -99,6 +115,8 @@ always @(posedge BUS_CLK) begin
             BUS_DATA_OUT <= {7'b0, CONF_DONE};
         else if(BUS_ADD == 8)
             BUS_DATA_OUT <= CONF_ERROR_LOST;
+//        else if (BUS_ADD == 12)
+//            BUS_DATA_OUT <= FEEDBACK_THRESHOLD_TRIGGERED;
         else if(BUS_ADD < 16)
             BUS_DATA_OUT <= BUS_STATUS_OUT;
     end
@@ -147,7 +165,7 @@ always @(posedge ADC_ENC) begin
 end
 
 wire start_data_count;
-assign start_data_count = (CONF_START_WITH_SYNC ? (adc_sync_wait && adc_sync_pulse) : start_adc_sync) || ( CONF_EN_EX_TRIGGER && ADC_TRIGGER);
+assign start_data_count = (CONF_START_WITH_SYNC ? (adc_sync_wait && adc_sync_pulse) : start_adc_sync) || ( CONF_EN_EX_TRIGGER && ADC_TRIGGER) || (CONF_TRIGGER_THRESHOLD && ADC_THRESHOLD);
 
 
 reg [23:0] rec_cnt;
@@ -202,11 +220,27 @@ always @(posedge ADC_ENC)
 always @(posedge ADC_ENC)
         adc_dly_mem <= dly_mem[dly_addr_read];
 
+reg status_LED_temp;
+
+
+
 always @(*) begin
+	 ADC_IN_DLY_BUF = ADC_IN_DLY;
     dly_addr_read = dly_addr_write - CONF_SAMPEL_DLY;
     ADC_IN_DLY = CONF_SAMPEL_DLY == 0 ? ADC_IN : adc_dly_mem;
+    if(CONF_TRIGGER_THRESHOLD==1 || CONF_TRIGGER_THRESHOLD==4) begin // MODE 1: Check if value is smaller than threshold
+		ADC_THRESHOLD = (ADC_IN_DLY < CONF_SET_TRIGGER_THRESHOLD); end
+    else if(CONF_TRIGGER_THRESHOLD==2) begin // MODE 2: Check if value exceeds threshold
+		ADC_THRESHOLD = (ADC_IN_DLY > CONF_SET_TRIGGER_THRESHOLD);end
+    else if(CONF_TRIGGER_THRESHOLD==3) begin// MODE 3: Check if value changes more than threshold
+		ADC_THRESHOLD = (ADC_IN_DLY_BUF-ADC_IN_DLY > CONF_SET_TRIGGER_THRESHOLD);end
+	if(ADC_THRESHOLD) begin
+		FEEDBACK_THRESHOLD_TRIGGERED = FEEDBACK_THRESHOLD_TRIGGERED+1; end
 end
-//
+
+assign status_LED = status_LED_temp;
+
+
 
 always @(posedge ADC_ENC) begin
         prev_data <= ADC_IN_DLY;
@@ -228,18 +262,22 @@ end
 
 reg [31:0] data_to_fifo;
 always @(*) begin
-    if(CONF_SINGLE_DATA)
-        data_to_fifo = {HEADER_ID, ADC_ID, CONF_EN_EX_TRIGGER ? rec_cnt == 1 : ADC_SYNC, 14'b0, ADC_IN_DLY};
-    else
+    if(CONF_SINGLE_DATA) begin
+        if (!CONF_TRIGGER_THRESHOLD)begin
+            data_to_fifo = {HEADER_ID, ADC_ID, CONF_EN_EX_TRIGGER ? rec_cnt == 1 : ADC_SYNC, 14'b0, ADC_IN_DLY};end
+		  else begin
+            data_to_fifo = {HEADER_ID, ADC_ID, CONF_TRIGGER_THRESHOLD ? (rec_cnt == 1) : ADC_SYNC, 14'b0, ADC_IN_DLY};end
+    end
+    else begin
         data_to_fifo = {HEADER_ID, ADC_ID, prev_sync, prev_data, ADC_IN_DLY};
+    end
 
     if(CONF_SINGLE_DATA)
         cdc_fifo_write = cdc_fifo_write_single;
     else
         cdc_fifo_write = cdc_fifo_write_double;
 
 end
-
 wire [31:0] cdc_data_out;
 cdc_syncfifo #(
     .DSIZE(32),

basil/firmware/modules/seq_gen/seq_gen.v

@@ -13,7 +13,7 @@ module seq_gen #(
     parameter ABUSWIDTH = 16,
 
     parameter MEM_BYTES = 16384,
-    parameter OUT_BITS = 8
+    parameter OUT_BITS = 16
 ) (
     input wire          BUS_CLK,
     input wire          BUS_RST,

basil/firmware/modules/seq_gen/seq_gen_blk_mem_16x8196.v

@@ -0,0 +1,162 @@
+/**
+ * ------------------------------------------------------------
+ * Copyright (c) All rights reserved 
+ * SiLab, Institute of Physics, University of Bonn
+ * ------------------------------------------------------------
+ */
+`timescale 1ps/1ps
+`default_nettype none
+
+module seq_gen_blk_mem (
+    clka, clkb, wea, addra, dina, web, addrb, dinb, douta, doutb
+);
+
+input wire clka;
+input wire clkb;
+input wire [0 : 0] wea;
+input wire [13 : 0] addra;
+input wire [7 : 0] dina;
+input wire [0 : 0] web;
+input wire [12 : 0] addrb;
+input wire [15 : 0] dinb;
+output wire [7 : 0] douta;
+output wire [15 : 0] doutb;
+
+RAMB16_S1_S2 mem0  (
+    .CLKA(clka),
+    .CLKB(clkb),
+    .ENB(1'b1),
+    .SSRB(1'b0),
+    .WEA(wea[0]),
+    .WEB(web[0]),
+    .ENA(1'b1),
+    .SSRA(1'b0),
+    .ADDRA(addra[13:0]),
+    .ADDRB(addrb[12:0]),
+    .DIA({dina[7]}),
+    .DIB({dinb[15], dinb[7]}),
+    .DOA({douta[7]}),
+    .DOB({doutb[15], doutb[7]})
+);
+
+RAMB16_S1_S2 mem1  (
+    .CLKA(clka),
+    .CLKB(clkb),
+    .ENB(1'b1),
+    .SSRB(1'b0),
+    .WEA(wea[0]),
+    .WEB(web[0]),
+    .ENA(1'b1),
+    .SSRA(1'b0),
+    .ADDRA(addra[13:0]),
+    .ADDRB(addrb[12:0]),
+    .DIA({dina[6]}),
+    .DIB({dinb[14], dinb[6]}),
+    .DOA({douta[6]}),
+    .DOB({doutb[14], doutb[6]})
+);
+
+RAMB16_S1_S2 mem2  (
+    .CLKA(clka),
+    .CLKB(clkb),
+    .ENB(1'b1),
+    .SSRB(1'b0),
+    .WEA(wea[0]),
+    .WEB(web[0]),
+    .ENA(1'b1),
+    .SSRA(1'b0),
+    .ADDRA(addra[13:0]),
+    .ADDRB(addrb[12:0]),
+    .DIA({dina[5]}),
+    .DIB({dinb[13], dinb[5]}),
+    .DOA({douta[5]}),
+    .DOB({doutb[13], doutb[5]})
+);
+
+RAMB16_S1_S2 mem3 (
+    .CLKA(clka),
+    .CLKB(clkb),
+    .ENB(1'b1),
+    .SSRB(1'b0),
+    .WEA(wea[0]),
+    .WEB(web[0]),
+    .ENA(1'b1),
+    .SSRA(1'b0),
+    .ADDRA(addra[13:0]),
+    .ADDRB(addrb[12:0]),
+    .DIA({dina[4]}),
+    .DIB({dinb[12], dinb[4]}),
+    .DOA({douta[4]}),
+    .DOB({doutb[12], doutb[4]})
+);
+
+RAMB16_S1_S2 mem4  (
+    .CLKA(clka),
+    .CLKB(clkb),
+    .ENB(1'b1),
+    .SSRB(1'b0),
+    .WEA(wea[0]),
+    .WEB(web[0]),
+    .ENA(1'b1),
+    .SSRA(1'b0),
+    .ADDRA(addra[13:0]),
+    .ADDRB(addrb[12:0]),
+    .DIA({dina[3]}),
+    .DIB({dinb[11], dinb[3]}),
+    .DOA({douta[3]}),
+    .DOB({doutb[11], doutb[3]})
+);
+
+RAMB16_S1_S2 mem5  (
+    .CLKA(clka),
+    .CLKB(clkb),
+    .ENB(1'b1),
+    .SSRB(1'b0),
+    .WEA(wea[0]),
+    .WEB(web[0]),
+    .ENA(1'b1),
+    .SSRA(1'b0),
+    .ADDRA(addra[13:0]),
+    .ADDRB(addrb[12:0]),
+    .DIA({dina[2]}),
+    .DIB({dinb[10], dinb[2]}),
+    .DOA({douta[2]}),
+    .DOB({doutb[10], doutb[2]})
+);
+
+RAMB16_S1_S2 mem6  (
+    .CLKA(clka),
+    .CLKB(clkb),
+    .ENB(1'b1),
+    .SSRB(1'b0),
+    .WEA(wea[0]),
+    .WEB(web[0]),
+    .ENA(1'b1),
+    .SSRA(1'b0),
+    .ADDRA(addra[13:0]),
+    .ADDRB(addrb[12:0]),
+    .DIA({dina[1]}),
+    .DIB({dinb[9], dinb[1]}),
+    .DOA({douta[1]}),
+    .DOB({doutb[9], doutb[1]})
+);
+
+RAMB16_S1_S2 mem7  (
+    .CLKA(clka),
+    .CLKB(clkb),
+    .ENB(1'b1),
+    .SSRB(1'b0),
+    .WEA(wea[0]),
+    .WEB(web[0]),
+    .ENA(1'b1),
+    .SSRA(1'b0),
+    .ADDRA(addra[13:0]),
+    .ADDRB(addrb[12:0]),
+    .DIA({dina[0]}),
+    .DIB({dinb[8], dinb[0]}),
+    .DOA({douta[0]}),
+    .DOB({doutb[8], doutb[0]})
+);
+
+endmodule
+