Pipelined-MIPS-Processor

This projects is a five stage pipelined MIPS processor with mitigation strategies to solve data and control hazards. It has been implemented and simulated on Vivado 2020.2 and coded entirely in Verilog. .

Instructions on how to open the Project

You can clone the folder in any suitable folder on your machine using the command

git clone https://github.com/Rohit-Mundada/Pipelined-MIPS-Processor.git

After clong the project, open the project in Xilinx Vivado software (minimum version required 2020.2 or higher). Or alternatively, you can also go inside

/Xilinx/ and double click on mips.xpr to automatically open in your Vivado Software.

Documentation

All the relevant documentation is present in the /Reports/ folder, along with a hand-drawn circuit of the whole processor.

Circuit Implementation using the Vivado Block Designer tool