GitHub - RamAIbot/Binary-Convolution-RTL: The project focusses developing a synthesizable RTL module for performing binary convolution of the input image. The project was done as a part of (ECE 564) ASIC and FPGA design course offered by North Carolina State University.

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The project focusses developing a synthesizable RTL module for performing binary convolution of the input image. The project was done as a part of (ECE 564) ASIC and FPGA design course offered by North Carolina State University.

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
report		report
result		result
synth		synth
v		v
464_564_project_2021_v4 (3).pdf		464_564_project_2021_v4 (3).pdf
newdesign_control signals.xlsx		newdesign_control signals.xlsx