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Tk/fault enable reset inverting #68

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Tk/fault enable reset inverting #68

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622d25a
fix enable pin
tonokip Nov 28, 2020
2cd1a9b
make fault latching. implement enable. also gate the outputs with reset.
tonokip Nov 28, 2020
fa89916
invert resetn_buf to reset_buf. move inverting config to effect all o…
tonokip Nov 29, 2020
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48 changes: 31 additions & 17 deletions src/microstepper/microstepper_top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -56,31 +56,34 @@ end

wire fault0 = (minimum_on_timer0 > 0) && overCurrent0;
wire fault1 = (minimum_on_timer1 > 0) && overCurrent1;
wire fault = fault0 | fault1;
wire fault_active = fault0 | fault1;
reg fault;
reg reset_buf;
reg enable_buf;

reg [1:0] s1r, s2r, s3r, s4r;
wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l;
wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l;

assign s_l[0] = !(phase_a1_l | fault);
assign s_l[1] = !(phase_a2_l | fault);
assign s_l[2] = !(phase_b1_l | fault);
assign s_l[3] = !(phase_b2_l | fault);
assign s_l[0] = config_invert_lowside ^ (phase_a1_l | fault | enable_buf | reset_buf);
assign s_l[1] = config_invert_lowside ^ (phase_a2_l | fault | enable_buf | reset_buf);
assign s_l[2] = config_invert_lowside ^ (phase_b1_l | fault | enable_buf | reset_buf);
assign s_l[3] = config_invert_lowside ^ (phase_b2_l | fault | enable_buf | reset_buf);

assign s_h[0] = !(phase_a1_h | fault);
assign s_h[1] = !(phase_a2_h | fault);
assign s_h[2] = !(phase_b1_h | fault);
assign s_h[3] = !(phase_b2_h | fault);
assign s_h[0] = config_invert_highside ^ (phase_a1_h | fault | enable_buf | reset_buf);
assign s_h[1] = config_invert_highside ^ (phase_a2_h | fault | enable_buf | reset_buf);
assign s_h[2] = config_invert_highside ^ (phase_b1_h | fault | enable_buf | reset_buf);
assign s_h[3] = config_invert_highside ^ (phase_b2_h | fault | enable_buf | reset_buf);

assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1]));
assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1]));
assign phase_a2_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1]));
assign phase_a2_l = config_invert_lowside ^ (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1]));
assign phase_a1_h = (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1]));
assign phase_a1_l = (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1]));
assign phase_a2_h = (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1]));
assign phase_a2_l = (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1]));

assign phase_b1_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1]));
assign phase_b1_l = config_invert_lowside ^ (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1]));
assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1]));
assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1]));
assign phase_b1_h = (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1]));
assign phase_b1_l = (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1]));
assign phase_b2_h = (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1]));
assign phase_b2_l = (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1]));

wire s1_starting = s1r == 2'b10;
wire s2_starting = s2r == 2'b10;
Expand All @@ -96,7 +99,18 @@ end
end
`endif

// Fault Conditions
always @(posedge clk) begin
if (!resetn)
fault <= 0;
else if( fault_active )
fault <= 1;
end

// Buffers
always @(posedge clk) begin
enable_buf <= enable;
reset_buf <= ~resetn;
s1r <= {s1r[0], s1};
s2r <= {s2r[0], s2};
s3r <= {s3r[0], s3};
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2 changes: 1 addition & 1 deletion src/top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -187,7 +187,7 @@ module top (

wire step;
wire dir;
reg enable;
reg enable = 0;

`ifdef DUAL_HBRIDGE
DualHBridge s0 (.phase_a1 (PHASE_A1[1]),
Expand Down