Merge pull request #112 from RAPcores/sjk/encharness1

Add encoder output to rapcore test harness

etc/reginit.sh

@@ -1,3 +1,7 @@
 #! /usr/bin/env bash
 
+# Reg initialization - disallowed
+
 grep -nrP '(reg)(.*)([=<])(.*)(;)' src/*
+
+grep -nrP '(.*)([=<])(.*)(;)' src/* | grep -v 'assign' | grep -v 'wire' | grep -v '<='

src/quad_enc.v

@@ -22,14 +22,16 @@ module quad_enc #(
   wire direction = a_stable[1] ^ b_stable[2];  //Direction determined by comparing current sample to last
 
   always @(posedge clk) begin
-    a_stable <= {a_stable[1:0], a};  //Shift new a in. Last 2 samples shift to bits 2 and 1
-    b_stable <= {b_stable[1:0], b};  //Shift new b in
-
     if (!resetn) begin
       count <= 0;  //reset count
-      faultn <= 1; //reset faultn
+      faultn <= 1'b1; //reset faultn
+      a_stable <= 3'b0;
+      b_stable <= 3'b0;
     end
     else begin
+      a_stable <= {a_stable[1:0], a};  //Shift new a in. Last 2 samples shift to bits 2 and 1
+      b_stable <= {b_stable[1:0], b};  //Shift new b in
+
       if (step_a && step_b)  //We do not know direction if both inputs triggered on single clock
         faultn <= 0;
       if (step) begin

src/spi_state_machine.v

@@ -72,7 +72,7 @@ module spi_state_machine(
   wire [63:0] word_data_received_w;
   always @(posedge spi_clock)
   if(!resetn)
-    word_data_received = 0;
+    word_data_received <= 0;
   else
     word_data_received <= word_data_received_w;
 
@@ -277,6 +277,17 @@ module spi_state_machine(
     message_word_count <= 0;
     message_header <= 0;
 
+    word_received_r <= 2'b0;
+
+    // TODO change to for loops
+    move_duration[0] <= 64'b0;
+    move_duration[1] <= 64'b0;
+    increment[0] <= 64'b0;
+    increment[1] <= 64'b0;
+    incrementincrement[0] <= 64'b0;
+    incrementincrement[1] <= 64'b0;
+    encoder_store <= 64'b0;
+
   end else if (resetn) begin
     word_received_r <= {word_received_r[0], word_received};
     if (word_received_r == 2'b01) begin
@@ -360,7 +371,7 @@ module spi_state_machine(
             word_send_data[23:16] <= `VERSION_MAJOR;
           end
 
-          default: word_send_data = 64'b0;
+          default: word_send_data <= 64'b0;
 
         endcase
 

testbench/rapcore_harness_tb.v

@@ -225,4 +225,27 @@ module rapcore_harness (
   );
 
 
+  //
+  // ENCODER
+  //
+
+  reg enca_r, encb_r;
+  reg [3:0] encct;
+  initial begin
+    enca_r <= 0;
+    encb_r <= 1;
+    encct <= 0;
+  end
+
+  assign ENC_B = encb_r;
+  assign ENC_A = enca_r;
+
+  // This is not tied to reality whatso ever
+  // just a quadrature wave for test
+  always @(posedge CLK) begin
+      encct <= encct + 1'b1; // slow it down a bit
+      if (&encct) enca_r <= ~enca_r;
+      if (encct == 4'b1000) encb_r <= ~encb_r;
+  end
+
 endmodule