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Merge pull request #84 from RAPcores/tb_m
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Tb m
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@sjkelly
sjkelly authored Dec 8, 2020
2 parents db0e512 + 767e1a7 commit 817ba5f
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Showing 22 changed files with 1,173 additions and 593 deletions.
8 changes: 6 additions & 2 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ GENERATEDDIR = ./src/generated/
SRCDIR = ./src/
BUILDDIR = ./build/
BUILD = $(BUILDDIR)$(BOARD)
RAPCOREFILES := boards/$(BOARD)/$(BOARD).v src/constants.v src/macro_params.v src/pwm.v src/quad_enc.v src/spi.v src/stepper.v src/dda_timer.v src/rapcore.v $(wildcard src/microstepper/*.v)
RAPCOREFILES := boards/$(BOARD)/$(BOARD).v src/constants.v src/macro_params.v src/spi_state_machine.v src/pwm.v src/quad_enc.v src/spi.v src/stepper.v src/dda_timer.v src/rapcore.v $(wildcard src/microstepper/*.v)

all: $(BUILD).bit

Expand Down Expand Up @@ -57,8 +57,12 @@ formal:
lint:
verible-verilog-lint src/*.v

testbench:
testbench_quad_encoder:
yosys sim.ys
gtkwave testbench/quad_enc.vcd
testbench_microstepper:
yosys sim_microstepper.ys
gtkwave testbench/microstepper.vcd

.SECONDARY:
.PHONY: all prog clean testbench formal
8 changes: 8 additions & 0 deletions sim_microstepper.tcl
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@@ -0,0 +1,8 @@
yosys -import

set

read_verilog -sv testbench/microstepper_tb.v src/microstepper/*.v
prep -top testbench
show m_control_0
sim -n 40000 -clock clk -vcd testbench/microstepper.vcd
14 changes: 14 additions & 0 deletions sim_microstepper.ys
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@@ -0,0 +1,14 @@

read_verilog -sv testbench/microstepper_tb.v \
src/microstepper/analog_out.v \
src/microstepper/chargepump.v \
src/microstepper/cosine.v \
src/microstepper/microstep_counter.v \
src/microstepper/microstepper_control.v \
src/microstepper/mytimer_8.v \
src/microstepper/mytimer_10.v \
src/microstepper/mytimer.v

prep -top testbench
show microstepper_top
sim -n 400000 -clock clk -vcd testbench/microstepper.vcd
8 changes: 6 additions & 2 deletions src/dda_timer.v
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Expand Up @@ -7,8 +7,8 @@ module dda_timer(
input [63:0] increment,
input [63:0] incrementincrement,
input [`MOVE_BUFFER_SIZE:0] stepready,
output reg [`MOVE_BUFFER_SIZE:0] stepfinished,
output reg [`MOVE_BUFFER_BITS:0] moveind, // DDA buffer index
output [`MOVE_BUFFER_SIZE:0] stepfinished,
output [`MOVE_BUFFER_BITS:0] moveind, // DDA buffer index
input [`MOVE_BUFFER_BITS:0] writemoveind, // State Machine index
output step,
`ifdef HALT
Expand All @@ -27,6 +27,10 @@ module dda_timer(
reg signed [63:0] increment_r;
reg finishedmove = 1; // flag inidicating a move has been finished, so load next

// Buffer managment
reg [`MOVE_BUFFER_BITS:0] moveind = 0; // Move index cursor
reg [`MOVE_BUFFER_SIZE:0] stepfinished = 0;

// State managment
wire processing_move = (stepfinished[moveind] ^ stepready[moveind]);
wire loading_move = finishedmove & processing_move;
Expand Down
19 changes: 12 additions & 7 deletions src/microstepper/analog_out.v
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Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module analog_out (
input wire clk,
input wire resetn,
Expand All @@ -10,13 +11,17 @@ module analog_out (

reg [10:0] pwm_counter;

always @(posedge clk)
if (resetn)
if (pwm_counter <= current_threshold)
pwm_counter <= pwm_counter + 1'b1;
else
pwm_counter <= 0;

always @(posedge clk) begin
if (!resetn) begin
pwm_counter <= 0;
end
else begin
if (pwm_counter <= current_threshold)
pwm_counter <= pwm_counter + 1'b1;
else
pwm_counter <= 0;
end
end
assign analog_out1 = pwm_counter <= pwm1;
assign analog_out2 = pwm_counter <= pwm2;

Expand Down
1 change: 1 addition & 0 deletions src/microstepper/chargepump.v
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@@ -1,3 +1,4 @@
`default_nettype none
module chargepump (
input clk,
input resetn,
Expand Down
207 changes: 66 additions & 141 deletions src/microstepper/cosine.v
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Original file line number Diff line number Diff line change
@@ -1,150 +1,75 @@
`default_nettype none
module cosine (
input wire [5:0] cos_index,
output wire [7:0] cos_value,
input wire [511:0] cos_table
output wire [7:0] cos_value
);

//reg [31:0] cos_table[0:255];

//assign cos_value = cos_table[cos_index*8+7:cos_index*8];

reg [7:0] cos_r;
assign cos_value = cos_r;

always @(*)
case (cos_index)
1'd0 : cos_r <= cos_table [ 7 : 0 ];
1'd1 : cos_r <= cos_table [ 15 : 8 ];
2'd2 : cos_r <= cos_table [ 23 : 16 ];
2'd3 : cos_r <= cos_table [ 31 : 24 ];
3'd4 : cos_r <= cos_table [ 39 : 32 ];
3'd5 : cos_r <= cos_table [ 47 : 40 ];
3'd6 : cos_r <= cos_table [ 55 : 48 ];
3'd7 : cos_r <= cos_table [ 63 : 56 ];
4'd8 : cos_r <= cos_table [ 71 : 64 ];
4'd9 : cos_r <= cos_table [ 79 : 72 ];
4'd10 : cos_r <= cos_table [ 87 : 80 ];
4'd11 : cos_r <= cos_table [ 95 : 88 ];
4'd12 : cos_r <= cos_table [ 103 : 96 ];
4'd13 : cos_r <= cos_table [ 111 : 104 ];
4'd14 : cos_r <= cos_table [ 119 : 112 ];
4'd15 : cos_r <= cos_table [ 127 : 120 ];
5'd16 : cos_r <= cos_table [ 135 : 128 ];
5'd17 : cos_r <= cos_table [ 143 : 136 ];
5'd18 : cos_r <= cos_table [ 151 : 144 ];
5'd19 : cos_r <= cos_table [ 159 : 152 ];
5'd20 : cos_r <= cos_table [ 167 : 160 ];
5'd21 : cos_r <= cos_table [ 175 : 168 ];
5'd22 : cos_r <= cos_table [ 183 : 176 ];
5'd23 : cos_r <= cos_table [ 191 : 184 ];
5'd24 : cos_r <= cos_table [ 199 : 192 ];
5'd25 : cos_r <= cos_table [ 207 : 200 ];
5'd26 : cos_r <= cos_table [ 215 : 208 ];
5'd27 : cos_r <= cos_table [ 223 : 216 ];
5'd28 : cos_r <= cos_table [ 231 : 224 ];
5'd29 : cos_r <= cos_table [ 239 : 232 ];
5'd30 : cos_r <= cos_table [ 247 : 240 ];
5'd31 : cos_r <= cos_table [ 255 : 248 ];
6'd32 : cos_r <= cos_table [ 263 : 256 ];
6'd33 : cos_r <= cos_table [ 271 : 264 ];
6'd34 : cos_r <= cos_table [ 279 : 272 ];
6'd35 : cos_r <= cos_table [ 287 : 280 ];
6'd36 : cos_r <= cos_table [ 295 : 288 ];
6'd37 : cos_r <= cos_table [ 303 : 296 ];
6'd38 : cos_r <= cos_table [ 311 : 304 ];
6'd39 : cos_r <= cos_table [ 319 : 312 ];
6'd40 : cos_r <= cos_table [ 327 : 320 ];
6'd41 : cos_r <= cos_table [ 335 : 328 ];
6'd42 : cos_r <= cos_table [ 343 : 336 ];
6'd43 : cos_r <= cos_table [ 351 : 344 ];
6'd44 : cos_r <= cos_table [ 359 : 352 ];
6'd45 : cos_r <= cos_table [ 367 : 360 ];
6'd46 : cos_r <= cos_table [ 375 : 368 ];
6'd47 : cos_r <= cos_table [ 383 : 376 ];
6'd48 : cos_r <= cos_table [ 391 : 384 ];
6'd49 : cos_r <= cos_table [ 399 : 392 ];
6'd50 : cos_r <= cos_table [ 407 : 400 ];
6'd51 : cos_r <= cos_table [ 415 : 408 ];
6'd52 : cos_r <= cos_table [ 423 : 416 ];
6'd53 : cos_r <= cos_table [ 431 : 424 ];
6'd54 : cos_r <= cos_table [ 439 : 432 ];
6'd55 : cos_r <= cos_table [ 447 : 440 ];
6'd56 : cos_r <= cos_table [ 455 : 448 ];
6'd57 : cos_r <= cos_table [ 463 : 456 ];
6'd58 : cos_r <= cos_table [ 471 : 464 ];
6'd59 : cos_r <= cos_table [ 479 : 472 ];
6'd60 : cos_r <= cos_table [ 487 : 480 ];
6'd61 : cos_r <= cos_table [ 495 : 488 ];
6'd62 : cos_r <= cos_table [ 503 : 496 ];
default : cos_r <= cos_table [ 511 : 504 ];
1'd0: cos_r <= 255;
1'd1: cos_r <= 255;
2'd2: cos_r <= 255;
2'd3: cos_r <= 254;
3'd4: cos_r <= 254;
3'd5: cos_r <= 253;
3'd6: cos_r <= 252;
3'd7: cos_r <= 251;
4'd8: cos_r <= 250;
4'd9: cos_r <= 249;
4'd10: cos_r <= 247;
4'd11: cos_r <= 246;
4'd12: cos_r <= 244;
4'd13: cos_r <= 242;
4'd14: cos_r <= 240;
4'd15: cos_r <= 238;
5'd16: cos_r <= 236;
5'd17: cos_r <= 233;
5'd18: cos_r <= 231;
5'd19: cos_r <= 228;
5'd20: cos_r <= 225;
5'd21: cos_r <= 222;
5'd22: cos_r <= 219;
5'd23: cos_r <= 215;
5'd24: cos_r <= 212;
5'd25: cos_r <= 208;
5'd26: cos_r <= 205;
5'd27: cos_r <= 201;
5'd28: cos_r <= 197;
5'd29: cos_r <= 193;
5'd30: cos_r <= 189;
5'd31: cos_r <= 185;
6'd32: cos_r <= 180;
6'd33: cos_r <= 176;
6'd34: cos_r <= 171;
6'd35: cos_r <= 167;
6'd36: cos_r <= 162;
6'd37: cos_r <= 157;
6'd38: cos_r <= 152;
6'd39: cos_r <= 147;
6'd40: cos_r <= 142;
6'd41: cos_r <= 136;
6'd42: cos_r <= 131;
6'd43: cos_r <= 126;
6'd44: cos_r <= 120;
6'd45: cos_r <= 115;
6'd46: cos_r <= 109;
6'd47: cos_r <= 103;
6'd48: cos_r <= 98;
6'd49: cos_r <= 92;
6'd50: cos_r <= 86;
6'd51: cos_r <= 80;
6'd52: cos_r <= 74;
6'd53: cos_r <= 68;
6'd54: cos_r <= 62;
6'd55: cos_r <= 56;
6'd56: cos_r <= 50;
6'd57: cos_r <= 44;
6'd58: cos_r <= 37;
6'd59: cos_r <= 31;
6'd60: cos_r <= 25;
6'd61: cos_r <= 19;
6'd62: cos_r <= 13;
default: cos_r <= 6;
endcase

/*
initial begin
cos_table[0] = 8'd255;
cos_table[1] = 8'd255;
cos_table[2] = 8'd255;
cos_table[3] = 8'd254;
cos_table[4] = 8'd254;
cos_table[5] = 8'd253;
cos_table[6] = 8'd252;
cos_table[7] = 8'd251;
cos_table[8] = 8'd250;
cos_table[9] = 8'd249;
cos_table[10] = 8'd247;
cos_table[11] = 8'd246;
cos_table[12] = 8'd244;
cos_table[13] = 8'd242;
cos_table[14] = 8'd240;
cos_table[15] = 8'd238;
cos_table[16] = 8'd236;
cos_table[17] = 8'd233;
cos_table[18] = 8'd231;
cos_table[19] = 8'd228;
cos_table[20] = 8'd225;
cos_table[21] = 8'd222;
cos_table[22] = 8'd219;
cos_table[23] = 8'd215;
cos_table[24] = 8'd212;
cos_table[25] = 8'd208;
cos_table[26] = 8'd205;
cos_table[27] = 8'd201;
cos_table[28] = 8'd197;
cos_table[29] = 8'd193;
cos_table[30] = 8'd189;
cos_table[31] = 8'd185;
cos_table[32] = 8'd180;
cos_table[33] = 8'd176;
cos_table[34] = 8'd171;
cos_table[35] = 8'd167;
cos_table[36] = 8'd162;
cos_table[37] = 8'd157;
cos_table[38] = 8'd152;
cos_table[39] = 8'd147;
cos_table[40] = 8'd142;
cos_table[41] = 8'd136;
cos_table[42] = 8'd131;
cos_table[43] = 8'd126;
cos_table[44] = 8'd120;
cos_table[45] = 8'd115;
cos_table[46] = 8'd109;
cos_table[47] = 8'd103;
cos_table[48] = 8'd98;
cos_table[49] = 8'd92;
cos_table[50] = 8'd86;
cos_table[51] = 8'd80;
cos_table[52] = 8'd74;
cos_table[53] = 8'd68;
cos_table[54] = 8'd62;
cos_table[55] = 8'd56;
cos_table[56] = 8'd50;
cos_table[57] = 8'd44;
cos_table[58] = 8'd37;
cos_table[59] = 8'd31;
cos_table[60] = 8'd25;
cos_table[61] = 8'd19;
cos_table[62] = 8'd13;
cos_table[63] = 8'd6;
end
*/
endmodule
1 change: 1 addition & 0 deletions src/microstepper/microstep_counter.v
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Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module microstep_counter (
input [7:0] pos,
output [5:0] cos_index1,
Expand Down
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