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fix(DM): enlarge master node addr width for standalone DM #3897

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merged 1 commit into from
Nov 20, 2024
Merged

fix(DM): enlarge master node addr width for standalone DM #3897

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2 changes: 2 additions & 0 deletions src/main/scala/device/standalone/StandAloneDebugModule.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,8 @@ class StandAloneDebugModule (
useTL, baseAddress, addrWidth, dataWidth, hartNum
) with HasMasterInterface {

def masterAddrWidth: Int = 48

def addressSet: AddressSet = p(DebugModuleKey).get.address

val debugModule = LazyModule(new DebugModule(hartNum)(p))
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6 changes: 4 additions & 2 deletions src/main/scala/device/standalone/StandAloneDevice.scala
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Expand Up @@ -35,13 +35,15 @@ import utils.VerilogAXI4Record

trait HasMasterInterface { this: StandAloneDevice =>

def masterAddrWidth: Int

protected val masternode = TLIdentityNode()
// tilelink master io
private val tlmaster = Option.when(useTL)(TLManagerNode(Seq(
TLSlavePortParameters.v1(
managers = Seq(
TLSlaveParameters.v1(
address = Seq(AddressSet(0, (BigInt(1) << addrWidth) - 1)),
address = Seq(AddressSet(0, (BigInt(1) << masterAddrWidth) - 1)),
regionType = RegionType.UNCACHED,
supportsGet = TransferSizes(1, p(SoCParamsKey).L3BlockSize),
supportsPutPartial = TransferSizes(1, p(SoCParamsKey).L3BlockSize),
Expand All @@ -60,7 +62,7 @@ trait HasMasterInterface { this: StandAloneDevice =>
AXI4SlavePortParameters(
slaves = Seq(
AXI4SlaveParameters(
address = Seq(AddressSet(0, (BigInt(1) << addrWidth) - 1)),
address = Seq(AddressSet(0, (BigInt(1) << masterAddrWidth) - 1)),
regionType = RegionType.UNCACHED,
supportsRead = TransferSizes(1, p(SoCParamsKey).L3BlockSize),
supportsWrite = TransferSizes(1, p(SoCParamsKey).L3BlockSize),
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