drivers: clk: sam: update main, generic and PLL clocks for Microchip sama7g54 #6651

TonyHan11 · 2024-01-29T07:00:21Z

No description provided.

TonyHan11 · 2024-01-29T07:45:19Z

Some definitions added in core/drivers/clk/sam/at91_pmc.h in #6630 are used by the files updated in this PR, please apply the commits in #6630 first before build.

jforissier

Comment on "drivers: clk: sam: update to support main system bus clock for sama7g5". Once addressed, please add to this commit:

Acked-by: Jerome Forissier <[email protected]>

jforissier · 2024-01-30T10:20:51Z

core/drivers/clk/sam/at91_master.c

+	struct clk_master *master = hw->priv;
+	size_t i = 0;
+
+	for (; i < hw->num_parents; i++)


for (i = 0; i < hw->num_parents; i++) (and please keep the initialization size_t i = 0; regardless).

etienne-lms · 2024-01-29T13:42:21Z

core/drivers/clk/sam/at91_master.c

+			return i;
+
+	EMSG("Can't get correct parent of clock \"%s\"", hw->name);
+	return -1;


Return type size_t is unsigned, should be changed.

etienne-lms · 2024-01-29T13:46:55Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+	uint8_t safe_div;
+};
+
+static inline bool sam9x60_pll_ready(vaddr_t base, int id)


remove inline keyword. Not needed from a source file, it's rather used only from header files.

etienne-lms · 2024-01-29T13:47:15Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+{
+	unsigned int status = io_read32(base + AT91_PMC_PLL_ISR0);
+
+	return !!(status & BIT(id));


return status & BIT(id); is enough.
Or even return io_read32(base + AT91_PMC_PLL_ISR0) & BIT(id);

core/drivers/clk/sam/clk-sam9x60-pll.c

+
+	freq = parent_rate * (frac->mul + 1) +
+		UDIV_ROUND_NEAREST((unsigned long long)parent_rate * frac->frac,
+				   (1 << 22));


etienne-lms · 2024-01-29T13:51:38Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+{
+	struct sam9x60_pll_core *core = &frac->core;
+	vaddr_t regmap = frac->core.base;
+	unsigned int val = 0, cfrac = 0, cmul = 0;


define 1 local variable per line.

etienne-lms · 2024-01-30T10:43:50Z

core/drivers/clk/sam/at91_master.c

+	io_write32(master->base + AT91_PMC_MCR_V2, master->id);
+	val = io_read32(master->base + AT91_PMC_MCR_V2);
+	master->parent = (val & AT91_PMC_MCR_V2_CSS_MSK)
+			>> AT91_PMC_MCR_V2_CSS_SHIFT;


- master->parent = (val & AT91_PMC_MCR_V2_CSS_MSK) - >> AT91_PMC_MCR_V2_CSS_SHIFT; + master->parent = (val & AT91_PMC_MCR_V2_CSS_MSK) >> + AT91_PMC_MCR_V2_CSS_SHIFT;

etienne-lms · 2024-01-30T10:44:52Z

core/drivers/clk/sam/at91_generated.c

+	unsigned int i = 0;
+
+	if (gck->mux_table) {
+		for (; i < 8; i++)


some comment as for previous commit: for (i = 0; i < 8; i++)

etienne-lms · 2024-01-30T10:45:24Z

core/drivers/clk/sam/at91_generated.c

+			if (gck->mux_table[i] == gck->parent_id)
+				return i;
+		EMSG("Can't get correct parent of clock \"%s\"", clk->name);
+		return -1;


size_t is unsigned.

core/drivers/clk/sam/clk-sam9x60-pll.c

+#define PLL_DIV_MAX		PLL_DIV_MASK
+#define PLL_DIV(reg)		((reg) & PLL_DIV_MASK)
+#define PLL_MUL(reg, layout) ({ \
+	typeof(layout) __layout = layout; \


etienne-lms · 2024-01-30T10:54:37Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+#define PLL_MUL_MASK(layout)	((layout)->mul_mask)
+#define PLL_MUL_MAX(layout)	(PLL_MUL_MASK(layout) + 1)
+#define PLL_ICPR_SHIFT(id)	((id) * 16)
+#define PLL_ICPR_MASK(id)	(0xffff << PLL_ICPR_SHIFT(id))


SHIFT_U64(0xffff, PLL_ICPR_SHIFT(id))

TonyHan11 · 2024-01-31T02:44:29Z

@etienne-lms Updated according to the comments, review tags added and rebased on the latest master branch, thank you very much.

TonyHan11 · 2024-01-31T02:53:41Z

Timeout added for waiting PLL clock ready.

etienne-lms · 2024-01-31T07:56:05Z

core/drivers/clk/sam/at91_master.c

+			return i;
+
+	EMSG("Can't get correct parent of clock \"%s\"", hw->name);
+	return 0;


0 seems a valid return index. I think it's safe to panic() here since this is not awaited.

etienne-lms · 2024-01-31T07:57:25Z

core/drivers/clk/sam/at91_generated.c

+			if (gck->mux_table[i] == gck->parent_id)
+				return i;
+		EMSG("Can't get correct parent of clock \"%s\"", clk->name);
+		return 0;


could safely panic here IMHO.

Can remove the useless return 0 instruction.
Ditto in clk_sama7g5_master_get_parent().

etienne-lms · 2024-01-31T07:59:12Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+	cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
+
+	if (sam9x60_frac_pll_ready(regmap, core->id) &&
+	    (cmul == frac->mul && cfrac == frac->frac))


could remove the inner parentheses:

if (sam9x60_frac_pll_ready(regmap, core->id) && cmul == frac->mul && cfrac == frac->frac)

etienne-lms · 2024-01-31T08:02:12Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+			AT91_PMC_PLL_UPDT_UPDATE | core->id);
+
+	while (!sam9x60_pll_ready(regmap, core->id))
+		if (timeout_elapsed(timeout))


I recommend to use IO_READ32_POLL_TIMEOUT() macro the handle case where this function is called from a threaded context that is rescheduled between sam9x60_pll_ready() call and timeout_elapsed() call.

etienne-lms · 2024-01-31T08:03:43Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+	 * divider that provide the closest rate to the requested one.
+	 */
+	nmul = rate / parent_rate;
+	nmul += (rate % parent_rate) / parent_rate;


I think (rate % parent_rate) / parent_rate will always be 0.

etienne-lms · 2024-01-31T08:04:42Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+					      (1 << 22));
+	}
+
+	/* Check if resulted rate is a valid.  */


- /* Check if resulted rate is a valid. */ + /* Check if resulted rate is a valid. */

etienne-lms · 2024-01-31T08:05:44Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+				AT91_PMC_PLL_UPDT_UPDATE | core->id);
+
+		while (!sam9x60_pll_ready(regmap, core->id))
+			;


handle timeout with IO_READ32_POLL_TIMEOUT()?

Thank for your comments.

Commits updated according to the comments expect the using of IO_READ32_POLL_TIMEOUT(). The reason is that udelay() is used in the macro and there will be an assert failure while booting.

udelay() depends on plat_get_freq() which requires the initialization of freq (done by early_init_late(get_freq_from_dt);). Some PLL clocks need to be initialized before calling get_freq_from_dt, once the delay is called with non-initialized freq an assert failure will occur.

etienne-lms · 2024-01-31T08:06:02Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+			AT91_PMC_PLL_UPDT_UPDATE | core->id);
+
+	while (!sam9x60_pll_ready(regmap, core->id))
+		;


ditto about timeout handling

etienne-lms · 2024-01-31T08:06:25Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+{
+	struct sam9x60_pll_core *core = &div->core;
+	vaddr_t regmap = core->base;
+	unsigned int val = 0, cdiv = 0;


unsigned int cdiv = 0; unsigned int val = 0;

TonyHan11 · 2024-02-04T02:54:23Z

Update AT91_PMC_MCR_V2_DIV to AT91_PMC_MCR_V2_DIV_MSK according to the macro name changed in #6630

TonyHan11 · 2024-02-04T05:53:10Z

Missing offset of PLL ISR register while adding WAIT_PLL_READY_TIMEOUT macro, fixed.

etienne-lms · 2024-02-02T11:38:03Z

core/drivers/clk/sam/at91_generated.c

+			if (gck->mux_table[i] == gck->parent_id)
+				return i;
+		EMSG("Can't get correct parent of clock \"%s\"", clk->name);
+		return 0;


Can remove the useless return 0 instruction.
Ditto in clk_sama7g5_master_get_parent().

etienne-lms · 2024-02-05T05:34:39Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+				AT91_PMC_PLL_UPDT_UPDATE | core->id);
+
+		if (WAIT_PLL_READY_TIMEOUT(regmap, core->id))
+			EMSG("PLL not ready");


ret = TEE_ERROR_xxx if WAIT_PLL_READY_TIMEOUT() returns true?

return TEE_ERROR_BUSY; added, thanks.

etienne-lms · 2024-02-05T05:36:36Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+			AT91_PMC_PLL_UPDT_UPDATE | core->id);
+
+	if (WAIT_PLL_READY_TIMEOUT(regmap, core->id))
+		EMSG("PLL not ready");


return an error to code sam9x60_div_pll_set() and sam9x60_div_pll_set_rate_chg()?

Update the return code.

etienne-lms · 2024-02-05T05:37:26Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+	struct sam9x60_div *div = hw->priv;
+	struct sam9x60_pll_core *core = &div->core;
+	vaddr_t regmap = core->base;
+	unsigned int val, cdiv;


unsigned int cdiv = 0; unsigned int val = 0;

etienne-lms · 2024-02-05T07:34:55Z

core/drivers/clk/sam/clk-sam9x60-pll.c

@@ -0,0 +1,517 @@
+// SPDX-License-Identifier: GPL-2.0+


license model issue

etienne-lms · 2024-02-05T07:35:14Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2019 Microchip Technology Inc.
+ *


can remove this empty inline comment line.

Removed the empty line and updated the license model, thanks.

etienne-lms · 2024-02-07T22:49:42Z

core/drivers/clk/sam/at91_master.c

+	master->chg_pid = chg_pid;
+	master->mux_table = mux_table;
+
+	io_write32(master->base + AT91_PMC_MCR_V2, master->id);


CI make builds fail on AT91_PMC_MCR_V2* macros not being defined.

The definitions of these macros are added in #6630, you can find them in core/drivers/clk/sam/at91_pmc.h.
It's better to integrate #6630 before this PR, thanks.

jforissier · 2024-02-08T08:52:58Z

Some definitions added in core/drivers/clk/sam/at91_pmc.h in #6630 are used by the files updated in this PR, please apply the commits in #6630 first before build.

That's not how it works. If you need a commit from another PR, please add it here too, and mention that it does not need to be reviewed here due to being in pending PR xxx. This way things are clear and CI can be trusted.

etienne-lms · 2024-02-08T23:57:07Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+			if (_c) \
+				break; \
+		} \
+		!(_c); \


I would replace !(_c); with !io_read32((base) + AT91_PMC_PLL_ISR0) & BIT(id);. Explanations in #6297 (comment).

I would also replace base and id arguments name with _base and _id.

_base and _id updated. The !(_c) not replaced due to interrupt status register AT91_PMC_PLL_ISR0 has read-clear behavior.

~~Then, you need to find another way to address the case where the TEE thread has been rescheduled while this macro is executing.~~

Edited: Discard this comment, it was stupid as your timeout detection based on a trial counter.

As delay by a timer/counter can not be used here, add wait_cycles() to determine the timeout.

etienne-lms · 2024-02-09T00:02:25Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+{
+	vaddr_t regmap = core->base;
+	uint32_t ena_msk = enable ? core->layout->endiv_mask : 0;
+	uint32_t ena_val = enable ? (1 << core->layout->endiv_shift) : 0;


uint32_t ena_val = enable ? BIT(core->layout->endiv_shift) : 0;

Updated, thanks.

etienne-lms · 2024-02-09T00:06:12Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+					  bool enable)
+{
+	vaddr_t regmap = core->base;
+	uint32_t ena_msk = enable ? core->layout->endiv_mask : 0;


nitpicking: s/ena_msk/enable_mask/

Replaced msk with mask.

etienne-lms · 2024-02-19T16:22:08Z

@TonyHan11, could you rebase your series now that #6630 is merged?

TonyHan11 · 2024-02-20T02:36:03Z

Rebased to the latest master branch with some minor fixes.

TonyHan11 · 2024-02-22T07:25:00Z

Last update of WAIT_PLL_READY_TIMEOUT macro introduced a failure of eth0 in u-boot, fixed by extending the timeout value.

etienne-lms · 2024-02-20T07:12:09Z

core/drivers/clk/sam/at91_master.c

+		free(master);
+		return NULL;
+	}
+	return hw;


nitpicking: we usually add an empty line before the final return instruction in a function block.

Empty lines added before each of the final return, thanks.

etienne-lms · 2024-02-20T10:19:10Z

core/drivers/clk/sam/at91_generated.c

@@ -140,6 +151,7 @@ struct clk *
 at91_clk_register_generated(struct pmc_data *pmc,
 			    const struct clk_pcr_layout *layout,
 			    const char *name, struct clk **parents,
+			    uint32_t *mux_table,


It seems mux_parent here is always a 8 cell array reference. I suggest you define that in the argument type, if applicable: s/uin32t_t *mux_parent/uint32_t mux_parent[8]/
This would ensure line 76 and 90 will not overflow gck->mux_table size.

From clk_generated_set_parent() above, gck->mux_table size is related to the number of possible parents for the clock. Maybe use this info in clk_generated_get_parent(), instead of 8?

Added mux_table_size variable after uint32_t *mux_table in the struct and use it to avoid accessing beyond gck->mux_table.

The mux_table is used for sama7g5 support as the clock source of sama7g5_gck are from different PLL. For sama5d2 the sources are fixed and no mux is used.

etienne-lms · 2024-02-22T08:44:21Z

core/drivers/clk/sam/at91_clk.h

@@ -186,6 +186,14 @@ at91_clk_register_master_div(struct pmc_data *pmc,
 			     const struct clk_master_layout *layout,
 			     const struct clk_master_charac *charac);

+struct clk *at91_clk_sama7g5_register_master(struct pmc_data *pmc,


It suggest that you state somewhere that both parent and mux_table have num_parents cells.

mux_table_size added and assigned equal to num_parents in at91_clk_register_generated().

An inline description comment could clarify that when mux_table is not NULL it shall hold num_parents cells. This is only a suggestion.

etienne-lms · 2024-02-23T10:05:20Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+					   parent_rate);
+
+		tmprate += UDIV_ROUND_NEAREST((uint64_t)nfrac * parent_rate,
+					      (1 << 22));


could remove the inner parentheses

etienne-lms · 2024-02-23T10:11:52Z

core/drivers/clk/sam/at91_generated.c

@@ -72,16 +73,30 @@ static TEE_Result clk_generated_set_parent(struct clk *clk, size_t index)
 	if (index >= clk_get_num_parents(clk))
 		return TEE_ERROR_BAD_PARAMETERS;

-	gck->parent_id = index;
+	if (gck->mux_table) {
+		if (index > gck->mux_table_size)


this function get read clk->num_parents hence I think it's not needed to duplicate that info in struct clk_generated.

etienne-lms · 2024-02-23T10:13:19Z

core/drivers/clk/sam/at91_clk.h

@@ -186,6 +186,14 @@ at91_clk_register_master_div(struct pmc_data *pmc,
 			     const struct clk_master_layout *layout,
 			     const struct clk_master_charac *charac);

+struct clk *at91_clk_sama7g5_register_master(struct pmc_data *pmc,


An inline description comment could clarify that when mux_table is not NULL it shall hold num_parents cells. This is only a suggestion.

TonyHan11 · 2024-02-26T03:13:18Z

Updated according to the comments, thank you @etienne-lms

etienne-lms · 2024-02-26T08:30:26Z

core/drivers/clk/sam/at91_clk.h

@@ -186,6 +186,17 @@ at91_clk_register_master_div(struct pmc_data *pmc,
 			     const struct clk_master_layout *layout,
 			     const struct clk_master_charac *charac);

+/*
+ * @mux_table: when mux_table is not NULL it shll hold 'num_prents' cells


* @mux_table: when @mux_table is not NULL it shall hold @num_parents cells

etienne-lms · 2024-02-26T08:32:47Z

core/drivers/clk/sam/at91_master.c

+	unsigned long div = 0;
+
+	div = UDIV_ROUND_NEAREST(parent_rate, rate);
+	if ((div > (1 << (MASTER_PRES_MAX - 1))) || (div & (div - 1)))


suggestion: s/div & (div - 1)/!IS_POWER_OF_TWO(div)/

etienne-lms · 2024-02-26T08:38:18Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+		wait_cycles(100); \
+	} \
+	!(_c); \
+})


add an indentation tab to each line

#define WAIT_PLL_READY_TIMEOUT(_base, _id) \ ({ \ uint32_t __timeout = 0; \ uint32_t _c = 0; \ \ while (__timeout++ < 500) { \ _c = io_read32((_base) + AT91_PMC_PLL_ISR0) & BIT(_id); \ if (_c) \ break; \ wait_cycles(100); \ } \ !(_c); \ })

etienne-lms · 2024-02-27T13:36:57Z

core/drivers/clk/sam/at91_generated.c

+	unsigned int i = 0;
+
+	if (gck->mux_table) {
+		for (i = 0; i < gck->mux_table_size; i++)


nitpicking: clk_generated_set_parent() relies on index >= clk_get_num_parents(clk) and here on gck->mux_table_size. For consistency, I think you could remove field mux_table_size from struct clk_generated and use clk_get_num_parents(clk) here also (or use straight clk->num_parents as done in clk_sama7g5_master_xxx()).

etienne-lms · 2024-02-27T13:41:51Z

core/drivers/clk/sam/clk-sam9x60-pll.c

+	typeof(layout) __layout = layout; \
+	\
+	(((reg) >> (__layout)->mul_shift) & (__layout)->mul_mask); \
+})


Add an indentation tab (and can drop a pair of parentheses):

#define PLL_MUL(reg, layout) \ ({ \ typeof(layout) __layout = layout; \ \ ((reg) >> (__layout)->mul_shift) & (__layout)->mul_mask; \ })

TonyHan11 · 2024-02-28T05:46:00Z

Updated according to the comments, thanks.

etienne-lms

Acked-by: Etienne Carriere <[email protected]> with this last comment addressed.

etienne-lms · 2024-02-28T08:16:27Z

core/drivers/clk/sam/at91_clk.h

@@ -186,6 +203,17 @@ at91_clk_register_master_div(struct pmc_data *pmc,
 			     const struct clk_master_layout *layout,
 			     const struct clk_master_charac *charac);

+/*
+ * @mux_table: when @mux_table is not NULL it shall hold @num_prents cells


s/@num_prents/@num_parents/

Updated and added Acked-by, thank you.

Add functions for configuring sama7g5 main system bus clock. Signed-off-by: Tony Han <[email protected]> Acked-by: Jerome Forissier <[email protected]> Acked-by: Etienne Carriere <[email protected]>

Add a mux table for select from different generic clock source. Signed-off-by: Tony Han <[email protected]> Acked-by: Jerome Forissier <[email protected]> Acked-by: Etienne Carriere <[email protected]>

As PLL is compatible for sama7g5 and sam9x60, add sam9x60 PLL functions for configuring sama7g5 PLL. Signed-off-by: Tony Han <[email protected]> Acked-by: Jerome Forissier <[email protected]> Acked-by: Etienne Carriere <[email protected]>

jforissier · 2024-02-28T10:18:40Z

IBART error ignored, branch needs re-basing.

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TonyHan11 added 3 commits February 28, 2024 16:38

drivers: clk: sam: update to support main system bus clock for sama7g5

690ae72

Add functions for configuring sama7g5 main system bus clock. Signed-off-by: Tony Han <[email protected]> Acked-by: Jerome Forissier <[email protected]> Acked-by: Etienne Carriere <[email protected]>

drivers: clk: sam: update to support generic clock for sama7g5

50b9a7e

Add a mux table for select from different generic clock source. Signed-off-by: Tony Han <[email protected]> Acked-by: Jerome Forissier <[email protected]> Acked-by: Etienne Carriere <[email protected]>

TonyHan11 force-pushed the sama7g5_clk_pll branch from d383e20 to 3d34ea7 Compare February 28, 2024 08:41

jforissier merged commit 4318c69 into OP-TEE:master Feb 28, 2024
6 of 7 checks passed

TonyHan11 deleted the sama7g5_clk_pll branch February 29, 2024 02:43

drivers: clk: sam: update main, generic and PLL clocks for Microchip sama7g54 #6651

drivers: clk: sam: update main, generic and PLL clocks for Microchip sama7g54 #6651

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TonyHan11 commented Jan 29, 2024

TonyHan11 commented Jan 29, 2024

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TonyHan11 commented Jan 31, 2024

TonyHan11 commented Jan 31, 2024

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TonyHan11 commented Feb 4, 2024

TonyHan11 commented Feb 4, 2024

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etienne-lms Feb 7, 2024 • edited Loading

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jforissier commented Feb 8, 2024

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etienne-lms Feb 20, 2024 • edited Loading

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etienne-lms commented Feb 19, 2024

TonyHan11 commented Feb 20, 2024

TonyHan11 commented Feb 22, 2024

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TonyHan11 commented Feb 26, 2024

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TonyHan11 commented Feb 28, 2024

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etienne-lms Feb 7, 2024 •

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etienne-lms Feb 20, 2024 •

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