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12 changes: 6 additions & 6 deletions content/_index.md
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<ol style="width:180%; text-align:justify;list-style-type:decimal;">
<li>Zeyu Wang*, Xiaowu He*, Xiangwen Zhuge, Shen Xu, Fan Dang, Jingao Xu and Zheng Yang
<b>"Enabling Network Diagnostics in Time-Sensitive Networking:Protocol, Algorithm, and Hardware"</b>, IEEE <b>IWQoS</b>, 2024.
<a href="http://tns.thss.tsinghua.edu.cn/ziggo/data/TSNCard.pdf" target="_blank">[PDF]</a>
<a href="/pdf/TSNCard.pdf" target="_blank">[PDF]</a>
</li>
<li>Xiangwen Zhuge, Xinjun Cai, Xiaowu He, Zeyu Wang, Fan Dang, Wang Xu and Zheng Yang
<b>"InNetScheduler:In-network scheduling for time- and event-triggered critical traffic in TSN"</b>, IEEE <b>INFOCOM</b>, 2024.
<a href="http://tns.thss.tsinghua.edu.cn/ziggo/data/InNetScheduler.pdf" target="_blank">[PDF]</a>
<a href="/pdf/InNetScheduler.pdf" target="_blank">[PDF]</a>
</li>
<li>Zeyu Wang, Jingao Xu, Xu Wang, Xiangwen Zhuge, Xiaowu He, Zheng Yang
<b>"Industrial Knee-jerk:In-Network Simultaneous Planning and Control on a TSN Switch"</b>, ACM <b>MobiSys</b>, 2023.
<a href="http://tns.thss.tsinghua.edu.cn/ziggo/data/industrial-knee-jerk.pdf" target="_blank">[PDF]</a>
<a href="/pdf/industrial-knee-jerk.pdf" target="_blank">[PDF]</a>
</li>
<li>Zheng Yang, Yi Zhao, Fan Dang, Xiaowu He, Jiahang Wu, Hao Cao, Zeyu Wang, Yunhao Liu
<b>"CaaS:Enabling Control-as-a-Service for Time-Sensitive Networking"</b>, IEEE <b>INFOCOM</b>, 2023.
<a href="http://tns.thss.tsinghua.edu.cn/ziggo/data/caas.pdf" target="_blank">[PDF]</a>
<a href="/pdf/caas.pdf" target="_blank">[PDF]</a>
</li>
<li>Xiaowu He, Xiangwen Zhuge, Fan Dang, Wang Xu, Zheng Yang
<b>"DeepScheduler:Enabling Flow-Aware Scheduling in Time-Sensitive Networking"</b>, IEEE <b>INFOCOM</b>, 2023.
<a href="http://tns.thss.tsinghua.edu.cn/ziggo/data/deepscheduler.pdf" target="_blank">[PDF]</a>
<a href="/pdf/deepscheduler.pdf" target="_blank">[PDF]</a>
</li>
<li>Yi Zhao, Zheng Yang, Xiaowu He, Jiahang Wu, Hao Cao, Liang Dong, Fan Dang, Yunhao Liu
<b>"E-TSN:Enabling Event-triggered Critical Traffic in Time-Sensitive Networking for Industrial Applications"</b>, IEEE <b>ICDCS</b>, 2022.
<a href="http://tns.thss.tsinghua.edu.cn/ziggo/data/e-tsn.pdf" target="_blank">[PDF]</a>
<a href="/pdf/e-tsn.pdf" target="_blank">[PDF]</a>
</li>
</ol>

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我们再次重申,使用或者开发ZIGGO-CaaS-Switch或者ZIGGO-Device是有较高门槛的,您必须掌握一定的软硬件知识。如果您之间没有任何的硬件开发经验,您可能需要慎重考虑自己是否适合这个项目,因为学习这些知识是非常花时间的。
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## 1. 运行脚本前,在batch.mjs中要配置好以下变量:
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## Reporting a bug
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## Table of Content
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## Before Start
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## 软件环境清单

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This repo contains source code to enable TSN/CaaS TSNPerf' time synchronization logic and set up packet generation plan.
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ZIGGO is implemented on ZYNQ-7000 SoC and exploits ZYNQ's both hardware and software programmability.
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## 目录

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There are two analysis methods for ZIGGO Device:

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我们再次重申,使用或者开发ZIGGO-CaaS-Switch或者ZIGGO-Device是有较高门槛的,您必须掌握一定的软硬件知识。如果您之间没有任何的硬件开发经验,您可能需要慎重考虑自己是否适合这个项目,因为学习这些知识是非常花时间的。
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## Reporting a bug
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This repo contains pre-build hardware & system rootfs to boot the **Zynq AX7021** FPGA board from SD card.
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## 软件环境清单

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This repo contains source code to enable CaaS Switches' time synchronization logic and set up TSN GCL (gate control list), switch forwarding rules (including to dual-DMA).
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The CaaS/TSN Switch is developed based on the ZYNQ platform. The diagram below shows the composition of the ZYNQ chip. ZYNQ mainly consists of a Processing System (PS) and Programmable Logic (PL). The PS and PL mainly communicate with each other through the high-performance Advanced eXtensible Interface (AXI), which is more efficient than using FPGA directly as a peripheral. The PS contains an ARM-based processor suitable for running applications, drivers, and operating systems, while the PL contains FPGA suitable for running low-level hardware logic with high real-time performance requirements.
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## 硬件准备
准备两台机器,一台作为发送方Publisher,一台作为接收方Recorder,每一台上的硬件需满足以下条件
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## 时间同步测试
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## 现有方案的局限

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详细报告请查看[这里](/tsnperf/report/switch_report.pdf)
详细报告请查看[这里](/pdf/switch_report.pdf)
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"mt-1",
"mt-10",
"mt-12",
"mt-16",
"mt-2",
"mt-24",
"mt-3",
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<!doctype html>
<!-- This site was created with Hugo Blox. https://hugoblox.com -->
<!-- Last Published: May 18, 2024 --><html lang="en-us" dir="ltr"
<!-- Last Published: May 19, 2024 --><html lang="en-us" dir="ltr"
data-wc-theme-default="light">

<head><script src="/livereload.js?mindelay=10&amp;v=2&amp;port=1313&amp;path=livereload" data-no-instant defer></script>
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<h2>Latest</h2>
<ul>

<li><a href="/switch/basic_knowledge/">🧠 基础知识列表</a></li>

<li><a href="/device/basic_knowledge/">🧠 基础知识列表</a></li>

<li><a href="/tsnperf/">ZIGGO TSNPerf</a></li>

<li><a href="/switch/">ZIGGO Switch</a></li>

<li><a href="/device/">ZIGGO Device</a></li>

<li><a href="/device/getting-started/">🆒 Getting start</a></li>
<li><a href="/switch/require/">👩🏼‍🏫 准备清单</a></li>

<li><a href="/switch/basic_knowledge/">🧠 基础知识列表</a></li>

<li><a href="/tsnperf/principle/">📈 TSNPerf 设计原理</a></li>

<li><a href="/switch/system_design/">🔨 System Design —— PL &amp; PS Co-operate</a></li>

<li><a href="/device/system-design/">🔨 System Design —— PL &amp; PS Co-operate</a></li>
<li><a href="/switch/hardware-build/">💪 Hardware:FPGA bitstream &amp; Petalinux system rootfs for TSN Evaluation Toolkit</a></li>

<li><a href="/device/ziggo_device_manual/">📕 ZIGGO Device使用手册</a></li>
<li><a href="/switch/software_build/">💦 Software:Time Sync &#43; Config for CaaS Switches</a></li>

<li><a href="/device/cnc_manual/">📕 CNC脚本使用指南</a></li>
<li><a href="/switch/contributing/">🎉 How to contribute</a></li>

</ul>

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<!doctype html>
<!-- This site was created with Hugo Blox. https://hugoblox.com -->
<!-- Last Published: May 18, 2024 --><html lang="en-us" dir="ltr"
<!-- Last Published: May 19, 2024 --><html lang="en-us" dir="ltr"
data-wc-theme-default="light">

<head><script src="/livereload.js?mindelay=10&amp;v=2&amp;port=1313&amp;path=livereload" data-no-instant defer></script>
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