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Merge branch 'master' into pr_relax_udp
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udif committed Apr 4, 2024
2 parents 307f54a + 9e15d4e commit 19e619a
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Showing 2 changed files with 47 additions and 3 deletions.
8 changes: 5 additions & 3 deletions source/ast/Statements.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2281,12 +2281,14 @@ Statement& ExpressionStatement::fromSyntax(Compilation& compilation,
ok = true;
break;
}
case ExpressionKind::Assignment:
if (auto timing = expr.as<AssignmentExpression>().timingControl)
stmtCtx.observeTiming(*timing);
case ExpressionKind::Assignment: {
const AssignmentExpression& ae = expr.as<AssignmentExpression>();
if (ae.isBlocking() && ae.timingControl)
stmtCtx.observeTiming(*ae.timingControl);

ok = true;
break;
}
case ExpressionKind::NewClass:
ok = true;
break;
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42 changes: 42 additions & 0 deletions tests/unittests/ast/MemberTests.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1723,6 +1723,48 @@ endmodule
CHECK(diags[5].code == diag::TimingInFuncNotAllowed);
}

TEST_CASE("always_ff timing (pass)") {
auto tree = SyntaxTree::fromText(R"(
module x;
reg a;
wire clk;
always_ff @(posedge clk)
a <= #1 1'b0;
endmodule
)");

Compilation compilation;
compilation.addSyntaxTree(tree);

auto& diags = compilation.getAllDiagnostics();
REQUIRE(diags.size() == 0);
}

TEST_CASE("always_ff timing (fail)") {
auto tree = SyntaxTree::fromText(R"(
module x1;
reg a;
wire clk;
always_ff @(posedge clk)
#1 a <= 1'b0;
endmodule
module x2;
reg a;
wire clk;
always_ff @(posedge clk)
a = #1 1'b0;
endmodule
)");

Compilation compilation;
compilation.addSyntaxTree(tree);

auto& diags = compilation.getAllDiagnostics();
REQUIRE(diags.size() == 2);
CHECK(diags[0].code == diag::BlockingInAlwaysFF);
CHECK(diags[1].code == diag::BlockingInAlwaysFF);
}

TEST_CASE("always_comb drivers within nested functions") {
auto tree = SyntaxTree::fromText(R"(
module m;
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