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Implementation of a 35-taps FIR filter on a FPGA

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Management and analysis of physical datasets (module A) project

AY 2021/2022 University of Padua

A 35-taps re-programmable Finite Impulse Response filter on FPGA

repository by Lorenzo Valentini

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Implementation of a 35-taps FIR filter on a FPGA

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VHDL 100.0%