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Fix runtime - switch order of N and L
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Aba committed Oct 24, 2023
1 parent 760448d commit c609dd7
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Showing 2 changed files with 12 additions and 11 deletions.
22 changes: 11 additions & 11 deletions c/runtime.h
Original file line number Diff line number Diff line change
Expand Up @@ -53,12 +53,12 @@ static inline void process_y(int val, int i_py, Bundle_t *p_bundle, int ip, int
return;
}

// ------ ADD BIAS ------
if (p_bundle->is_bias)
val = (val << p_bundle->b_val_shift) + (mem.b[it_bias] << p_bundle->b_bias_shift);
// // ------ ADD BIAS ------
// if (p_bundle->is_bias)
// val = (val << p_bundle->b_val_shift) + (mem.b[it_bias] << p_bundle->b_bias_shift);

// ------ CORE ACT ------
val = quant_lrelu(val, p_bundle->ca_nzero, p_bundle->ca_shift, p_bundle->ca_pl_scale);
// // ------ CORE ACT ------
// val = quant_lrelu(val, p_bundle->ca_nzero, p_bundle->ca_shift, p_bundle->ca_pl_scale);


// ------ MAX/AVG POOL ------
Expand Down Expand Up @@ -120,10 +120,10 @@ extern EXT_C void load_y (unsigned char *p_done, unsigned char *pt_done_proc, c
// inverted to increment once per call
++iw; if (iw >= p_bundle->w_kw2) { iw = 0;
//after_each(in) = after_all(iw):
++in; if (in >= p_bundle->n) { in = 0;
//after_each(il) = after_all(in):
++il; if (il >= p_bundle->l) { il = 0;
//after_each(it) = after_all(il):
++il; if (il >= p_bundle->l) { il = 0;
//after_each(in) = after_all(il):
++in; if (in >= p_bundle->n) { in = 0;
//after_each(it) = after_all(in):
++it; if (it >= p_bundle->t) { it = 0;
//after_each(ip) = after_all(it):
printf("done p!! iw:%d in:%d il:%d it:%d ip:%d ib:%d\n", iw, in, il, it, ip, ib);
Expand All @@ -146,8 +146,8 @@ extern EXT_C void load_y (unsigned char *p_done, unsigned char *pt_done_proc, c
i_py = 0;
}//new(it):
it_bias = p_bundle->b_offset + p_bundle->coe*it;
}//new(il):
}//new(in):
}//new(in):
}//new(il):
}//new(iw):
*pt_done_proc = !(*pt_done_proc);
}
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1 change: 1 addition & 0 deletions test/py/bundle.py
Original file line number Diff line number Diff line change
Expand Up @@ -263,6 +263,7 @@ def add (p, p_frac, p_bits, q, q_frac, q_bits):
clog2_add = int(np.ceil(np.log2(np.prod(self.w['int'].shape[:-1]))))
self.proc['bits'] = self.inp['bits'] + self.w['bits'] + clog2_add
self.proc['frac'] = self.inp['frac'] + self.w['frac']
# self.o_exp = self.proc['int']

if self.b is not None:
(self.proc['int'], self.proc['frac'], self.proc['bits']), (self.bias_val_shift, self.bias_b_shift) = add(
Expand Down

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