Skip to content

Commit

Permalink
Fix verilator warnings - all except w_m_ready loop
Browse files Browse the repository at this point in the history
  • Loading branch information
Aba committed Nov 29, 2023
1 parent b82bdf2 commit 91066c8
Show file tree
Hide file tree
Showing 11 changed files with 65 additions and 196 deletions.
2 changes: 1 addition & 1 deletion .github/workflows/verify.yml
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ jobs:
- name: Install Verilator
run: |
sudo apt-get install git help2man perl python3 make autoconf g++ flex bison ccache libunwind-dev
sudo apt-get install libgoogle-perftools-dev numactl perl-doc
sudo apt-get install libgoogle-perftools-dev numactl #perl-doc
sudo apt-get install libfl2 # Ubuntu only (ignore if gives error)
sudo apt-get install libfl-dev # Ubuntu only (ignore if gives error)
# sudo apt-get install zlibc zlib1g zlib1g-dev # Ubuntu only (ignore if gives error)
Expand Down
6 changes: 3 additions & 3 deletions deepsocflow/c/runtime.h
Original file line number Diff line number Diff line change
Expand Up @@ -481,8 +481,8 @@ extern EXT_C void load_y (uint8_t *p_done, uint64_t *p_base_addr_next, int32_t *
FILE *fp_tiled = fopen(f_path_tiled, "w");
for (int32_t i=0; i<pb->o_words; i++)
if (ib == N_BUNDLES-1)
if (pb->is_softmax) fprintf(fp_tiled,"%f\n", mem.y[i]);
else fprintf(fp_tiled,"%d\n", mem.y[i]);
if (pb->is_softmax) fprintf(fp_tiled,"%f\n", (float )mem.y[i]);
else fprintf(fp_tiled,"%d\n", (int32_t)mem.y[i]);
else fprintf(fp_tiled,"%d\n", mem.debug_tiled[i]);
fclose(fp_tiled);

Expand Down Expand Up @@ -555,7 +555,7 @@ extern EXT_C void fill_memory (uint64_t *p_w_base, uint64_t *p_x_base){
fp = fopen(f_path, "rb");
if(!fp)
printf("ERROR! File not found: %s \n", f_path);
fread(mem.w, 1, WB_BYTES+X_BYTES, fp);
int bytes = fread(mem.w, 1, WB_BYTES+X_BYTES, fp);
fclose(fp);

for (int32_t i=0; i<B_WORDS; i++)
Expand Down
2 changes: 1 addition & 1 deletion deepsocflow/py/hardware.py
Original file line number Diff line number Diff line change
Expand Up @@ -199,7 +199,7 @@ def simulate(self, SIM='verilator', SIM_PATH=''):
assert subprocess.run(cmd).returncode == 0

if SIM == "verilator":
cmd = f'{SIM_PATH}verilator --binary -j 0 -Wno-fatal --trace --relative-includes --top {self.TB_MODULE} -I../ -F ../sources.txt -CFLAGS -I../ {self.MODULE_DIR}/c/example.c --Mdir ./'
cmd = f'{SIM_PATH}verilator --binary -j 0 -Wno-fatal -Wno-WIDTHEXPAND --trace --relative-includes --top {self.TB_MODULE} -I../ -F ../sources.txt -CFLAGS -I../ {self.MODULE_DIR}/c/example.c --Mdir ./'
print(cmd)
assert subprocess.run(cmd.split(' '), cwd='build').returncode == 0

Expand Down
21 changes: 14 additions & 7 deletions deepsocflow/rtl/axis_pixels.sv
Original file line number Diff line number Diff line change
Expand Up @@ -53,10 +53,17 @@ module axis_pixels #(
.s_axis_tvalid (dw_s_valid ),
.s_axis_tlast (s_last ),
.s_axis_tready (dw_s_ready ),
.s_axis_tid ('0),
.s_axis_tdest ('0),
.s_axis_tuser ('0),
.m_axis_tdata (dw_m_data ),
.m_axis_tready (dw_m_ready ),
.m_axis_tvalid (dw_m_valid ),
.m_axis_tlast (dw_m_last )
.m_axis_tlast (dw_m_last ),
.m_axis_tid (),
.m_axis_tdest (),
.m_axis_tkeep (),
.m_axis_tuser ()
);

// State machine
Expand All @@ -67,8 +74,8 @@ module axis_pixels #(
logic [BITS_CI -1:0] ref_ci_in;
logic [BITS_XW -1:0] ref_w_in ;
logic [BITS_IM_BLOCKS-1:0] ref_l_in ;

assign {ref_l_in, ref_w_in, ref_ci_in, ref_kh2_in} = s_data;
localparam BITS_REF = BITS_IM_BLOCKS + BITS_XW + BITS_CI + BITS_KH2;
assign {ref_l_in, ref_w_in, ref_ci_in, ref_kh2_in} = BITS_REF'(s_data);

wire dw_m_last_beat = dw_m_valid && dw_m_ready && dw_m_last;
wire s_last_beat = s_valid && s_ready && s_last;
Expand Down Expand Up @@ -118,10 +125,10 @@ module axis_pixels #(
end

// Counters: KH, CI, W, Blocks
counter #(.W(BITS_KH) ) C_KH (.clk(aclk), .reset(en_config), .en(en_kh ), .max_in(BITS_KH'(ref_kh2_in*2)), .last_clk(last_clk_kh ), .last(last_kh));
counter #(.W(BITS_CI) ) C_CI (.clk(aclk), .reset(en_config), .en(last_clk_kh), .max_in(ref_ci_in ), .last_clk(last_clk_ci ));
counter #(.W(BITS_XW) ) C_W (.clk(aclk), .reset(en_config), .en(last_clk_ci), .max_in(ref_w_in ), .last_clk(last_clk_w ));
counter #(.W(BITS_IM_BLOCKS)) C_L (.clk(aclk), .reset(en_config), .en(last_clk_w ), .max_in(ref_l_in ), .last (last_l ), .first(first_l));
counter #(.W(BITS_KH) ) C_KH (.clk(aclk), .reset(en_config), .en(en_kh ), .max_in(BITS_KH'(ref_kh2_in*2)), .last_clk(last_clk_kh ), .last(last_kh),.first(), .count());
counter #(.W(BITS_CI) ) C_CI (.clk(aclk), .reset(en_config), .en(last_clk_kh), .max_in(ref_ci_in ), .last_clk(last_clk_ci ), .last(), .first(), .count());
counter #(.W(BITS_XW) ) C_W (.clk(aclk), .reset(en_config), .en(last_clk_ci), .max_in(ref_w_in ), .last_clk(last_clk_w ), .last(), .first(), .count());
counter #(.W(BITS_IM_BLOCKS)) C_L (.clk(aclk), .reset(en_config), .en(last_clk_w ), .max_in(ref_l_in ), .last_clk(), .last(last_l), .first(first_l),.count());

// RAM
logic [$clog2(RAM_EDGES_DEPTH) -1:0] ram_addr, ram_addr_r, ram_addr_in;
Expand Down
38 changes: 29 additions & 9 deletions deepsocflow/rtl/axis_weight_rotator.sv
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ module axis_weight_rotator #(
BRAM_WIDTH = M_WIDTH ,
BRAM_DEPTH = RAM_WEIGHTS_DEPTH ,
BITS_ADDR = $clog2(RAM_WEIGHTS_DEPTH ),
BITS_CONFIG_BEATS = $clog2(CONFIG_BEATS+1)
BITS_CONFIG_BEATS = $clog2(CONFIG_BEATS)+1
)(

input logic aclk,
Expand Down Expand Up @@ -71,7 +71,7 @@ module axis_weight_rotator #(
config_st s_config, count;
logic [1:0][BITS_ADDR + BITS_XN + BITS_IM_BLOCKS + BITS_XW + BITS_CI + BITS_KW2 -1:0] ref_config;

assign s_config = s_axis_tdata;
assign s_config = config_st'(s_axis_tdata);
wire s_handshake = s_axis_tready && s_axis_tvalid;
wire s_last_handshake = s_handshake && s_axis_tlast;

Expand All @@ -97,7 +97,15 @@ module axis_weight_rotator #(
.m_axis_tvalid (dw_m_valid ),
.m_axis_tready (dw_m_ready ),
.m_axis_tdata (dw_m_data_flat ),
.m_axis_tlast (dw_m_last )
.m_axis_tlast (dw_m_last ),
// Extras
.s_axis_tid ('0),
.s_axis_tdest ('0),
.s_axis_tuser ('0),
.m_axis_tid (),
.m_axis_tdest (),
.m_axis_tkeep (),
.m_axis_tuser ()
);

wire dw_m_handshake = dw_m_valid && dw_m_ready;
Expand Down Expand Up @@ -281,7 +289,19 @@ module axis_weight_rotator #(
.s_axis_tvalid(bram_m_valid),
.m_axis_tdata (m_axis_tdata),
.m_axis_tvalid(bram_reg_m_valid),
.m_axis_tready(bram_m_ready[i_read])
.m_axis_tready(bram_m_ready[i_read]),
// Unused
.s_axis_tkeep ('0),
.s_axis_tlast ('0),
.s_axis_tid ('0),
.s_axis_tdest ('0),
.s_axis_tuser ('0),
.s_axis_tready(),
.m_axis_tkeep (),
.m_axis_tlast (),
.m_axis_tid (),
.m_axis_tdest (),
.m_axis_tuser ()
);

// Counters
Expand All @@ -292,12 +312,12 @@ module axis_weight_rotator #(
assign ref_i_read = ref_config[i_read];

wire [BITS_CONFIG_BEATS-1:0] config_beats_const = CONFIG_BEATS-1;
counter #(.W(BITS_CONFIG_BEATS)) C_CONFIG (.clk(aclk), .reset(copy_config), .en(en_count_config), .max_in( config_beats_const ), .last_clk(lc_config), .last(l_config) );
counter #(.W(BITS_KW )) C_KW (.clk(aclk), .reset(copy_config), .en(en_kw ), .max_in(BITS_KW '( 2*ref_i_read.kw2 )), .last_clk(lc_kw ), .last(l_kw ), .first(f_kw ) );
counter #(.W(BITS_CI )) C_CI (.clk(aclk), .reset(copy_config), .en(lc_kw ), .max_in(BITS_CI '( ref_i_read.cin_1 )), .last_clk(lc_cin ), .last(l_cin ), .first(f_cin ) );
counter #(.W(BITS_CONFIG_BEATS)) C_CONFIG (.clk(aclk), .reset(copy_config), .en(en_count_config), .max_in( config_beats_const ), .last_clk(lc_config), .last(l_config), .first(), .count() );
counter #(.W(BITS_KW )) C_KW (.clk(aclk), .reset(copy_config), .en(en_kw ), .max_in(BITS_KW '( 2*ref_i_read.kw2 )), .last_clk(lc_kw ), .last(l_kw ), .first(f_kw ), .count() );
counter #(.W(BITS_CI )) C_CI (.clk(aclk), .reset(copy_config), .en(lc_kw ), .max_in(BITS_CI '( ref_i_read.cin_1 )), .last_clk(lc_cin ), .last(l_cin ), .first(f_cin ), .count() );
counter #(.W(BITS_XW )) C_XW (.clk(aclk), .reset(copy_config), .en(lc_cin ), .max_in(BITS_XW '( ref_i_read.cols_1 )), .last_clk(lc_cols ), .last(l_cols ), .first(f_cols ), .count(c_cols));
counter #(.W(BITS_IM_BLOCKS )) C_IM_BLOCKS (.clk(aclk), .reset(copy_config), .en(lc_cols ), .max_in(BITS_IM_BLOCKS '( ref_i_read.blocks_1)), .last_clk(lc_blocks), .last(l_blocks) );
counter #(.W(BITS_XN )) C_XN (.clk(aclk), .reset(copy_config), .en(lc_blocks ), .max_in(BITS_XN '( ref_i_read.xn_1 )), .last_clk(lc_xn ), .last(l_xn ) );
counter #(.W(BITS_IM_BLOCKS )) C_IM_BLOCKS (.clk(aclk), .reset(copy_config), .en(lc_cols ), .max_in(BITS_IM_BLOCKS '( ref_i_read.blocks_1)), .last_clk(lc_blocks), .last(l_blocks), .first(), .count() );
counter #(.W(BITS_XN )) C_XN (.clk(aclk), .reset(copy_config), .en(lc_blocks ), .max_in(BITS_XN '( ref_i_read.xn_1 )), .last_clk(lc_xn ), .last(l_xn ), .first(), .count() );

// Last & User

Expand Down
12 changes: 10 additions & 2 deletions deepsocflow/rtl/dnn_engine.v
Original file line number Diff line number Diff line change
Expand Up @@ -120,6 +120,7 @@ module dnn_engine #(
.m_ready (m_ready ),
.m_valid (m_valid ),
.m_data (m_data ),
.m_last_pkt (),
.m_last (m_last )
);

Expand Down Expand Up @@ -152,11 +153,17 @@ module dnn_engine #(
.s_axis_tdata (m_data_padded),
.s_axis_tlast (m_last ),
.s_axis_tkeep ({(Y_BITS_PADDED*ROWS/8){1'b1}}),
.s_axis_tid ('0 ),
.s_axis_tdest ('0 ),
.s_axis_tuser ('0 ),
.m_axis_tready (m_axis_tready),
.m_axis_tvalid (m_axis_tvalid),
.m_axis_tdata (m_axis_tdata ),
.m_axis_tlast (m_axis_tlast ),
.m_axis_tkeep (m_axis_tkeep )
.m_axis_tkeep (m_axis_tkeep ),
.m_axis_tid (),
.m_axis_tdest (),
.m_axis_tuser ()
);
endmodule

Expand Down Expand Up @@ -213,7 +220,8 @@ module proc_engine_out #(
.m_valid (m_valid ),
.m_data (m_data ),
.m_last_pkt (m_last_pkt ),
.m_last (m_last )
.m_last (m_last ),
.m_user ()
);

endmodule
4 changes: 2 additions & 2 deletions deepsocflow/rtl/ext/alex_axis_adapter.v
Original file line number Diff line number Diff line change
Expand Up @@ -260,8 +260,8 @@ end else begin : downsize
if (!m_axis_tvalid_reg || m_axis_tready) begin
// output register empty

m_axis_tdata_reg <= s_axis_tvalid_reg ? s_axis_tdata_reg : s_axis_tdata;
m_axis_tkeep_reg <= s_axis_tvalid_reg ? s_axis_tkeep_reg : s_axis_tkeep;
m_axis_tdata_reg <= s_axis_tvalid_reg ? M_DATA_WIDTH'(s_axis_tdata_reg) : M_DATA_WIDTH'(s_axis_tdata);
m_axis_tkeep_reg <= s_axis_tvalid_reg ? M_KEEP_WIDTH'(s_axis_tkeep_reg) : M_KEEP_WIDTH'(s_axis_tkeep);
m_axis_tlast_reg <= 1'b0;
m_axis_tid_reg <= s_axis_tvalid_reg ? s_axis_tid_reg : s_axis_tid;
m_axis_tdest_reg <= s_axis_tvalid_reg ? s_axis_tdest_reg : s_axis_tdest;
Expand Down
17 changes: 2 additions & 15 deletions deepsocflow/rtl/ext/alex_axis_adapter_any.sv
Original file line number Diff line number Diff line change
Expand Up @@ -36,21 +36,8 @@ module alex_axis_adapter_any #(
);

function integer lcm (input integer x, input integer y);
logic found = 0;
integer max, min, i;
if (x > y) begin
max = x;
min = y;
end else begin
max = y;
min = x;
end

for (i=max; i <= x*y; i=i+max)
if ( !found && (i % min == 0)) begin
lcm = i;
found = 1;
end
for (int m=x*y; m >= x; m=m-x) // Every multiple of x from x*y down to x
if (m % y == 0) lcm = m; // Return the smallest multiple of x that is divisible by y
endfunction

localparam I_DATA_WIDTH = lcm(S_DATA_WIDTH, M_DATA_WIDTH);
Expand Down
153 changes: 0 additions & 153 deletions deepsocflow/rtl/out_ram_switch.sv

This file was deleted.

2 changes: 1 addition & 1 deletion deepsocflow/test/sv/dma.sv
Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ module DMA_S2M #(
set_byte(base_addr + i_bytes, m_data[i]);
i_bytes += 1;
end
if (m_last) done <= 1;
if (m_last) done = 1;
end

#10ps // delay before writing
Expand Down
Loading

0 comments on commit 91066c8

Please sign in to comment.