Major Restructure: Move RTL,TCL,TB to deepsocflow for deployment. Kee…

…p config and build files outside
KastnerRG · Nov 16, 2023 · 6290620 · 6290620
1 parent 8a5eb2e
commit 6290620
Show file tree

Hide file tree

Showing 65 changed files with 100 additions and 145 deletions.
diff --git a/.github/workflows/verify.yml b/.github/workflows/verify.yml
@@ -45,6 +45,8 @@ jobs:
         export PATH=${VERILATOR_ROOT}/bin:${PATH}
         export PYMTL_VERILATOR_INCLUDE_DIR=${VERILATOR_ROOT}/share/verilator/include
         verilator --version
-        
-        cd test
-        python -m pytest -s py/param_test.py
+
+        pip install .
+        mkdir -p run/work
+        cd run/work
+        python -m pytest -s ../param_test.py
diff --git a/.gitignore b/.gitignore
@@ -1,26 +1,27 @@
 old/
 __pycache__
 
-fpga/*
-!fpga/scripts
+run/fpga/*
 
-asic/*
-!asic/scripts
-!asic/reports
+run/asic/*
+!deepsocflow/asic/reports
 
 *.pickle
-test/vectors
-test/xsim
-test/dnn_engine_tb.vcd
-test/xsc*
-test/obj_dir
-test/models
-test/temp
+deepsocflow/test/vectors
+deepsocflow/test/xsim
+deepsocflow/test/dnn_engine_tb.vcd
+deepsocflow/test/xsc*
+deepsocflow/test/obj_dir
+deepsocflow/test/models
+deepsocflow/test/temp
 
-test/py/*
+deepsocflow/test/py/*
 
 .svls.toml
 
+run/work/vectors/*
+run/work/build/*
+
 
 # Distribution / packaging
 .Python
@@ -50,6 +51,11 @@ MANIFEST
 
 # Sphinx documentation
 docs/**
+!docs/source
+docs/source/**
 !docs/source/conf.py
-!docs/source/index.rst
-!docs/source/modules.rst
+!docs/source/*.rst
+
+# VSCode
+settings.json
+.vscode
diff --git a/deepsocflow/__init__.py b/deepsocflow/__init__.py
@@ -1,2 +1,2 @@
-from deepsocflow.py.hardware import *
-from deepsocflow.py.utils import *
+from . import py
+from .py import *
diff --git a/asic/constraints/dnn_engine.sdc → deepsocflow/asic/constraints/dnn_engine.sdc b/asic/constraints/dnn_engine.sdc → deepsocflow/asic/constraints/dnn_engine.sdc
diff --git a/asic/constraints/proc_engine_out.sdc → ...flow/asic/constraints/proc_engine_out.sdc b/asic/constraints/proc_engine_out.sdc → ...flow/asic/constraints/proc_engine_out.sdc
diff --git a/asic/scripts/clock.tcl → deepsocflow/asic/scripts/clock.tcl b/asic/scripts/clock.tcl → deepsocflow/asic/scripts/clock.tcl
diff --git a/asic/scripts/initialFloorplan.tcl → ...socflow/asic/scripts/initialFloorplan.tcl b/asic/scripts/initialFloorplan.tcl → ...socflow/asic/scripts/initialFloorplan.tcl
diff --git a/asic/scripts/loadDesignTech.tcl → deepsocflow/asic/scripts/loadDesignTech.tcl b/asic/scripts/loadDesignTech.tcl → deepsocflow/asic/scripts/loadDesignTech.tcl
diff --git a/asic/scripts/outputGen.tcl → deepsocflow/asic/scripts/outputGen.tcl b/asic/scripts/outputGen.tcl → deepsocflow/asic/scripts/outputGen.tcl
diff --git a/asic/scripts/pinPlacement.tcl → deepsocflow/asic/scripts/pinPlacement.tcl b/asic/scripts/pinPlacement.tcl → deepsocflow/asic/scripts/pinPlacement.tcl
diff --git a/asic/scripts/placement.tcl → deepsocflow/asic/scripts/placement.tcl b/asic/scripts/placement.tcl → deepsocflow/asic/scripts/placement.tcl
diff --git a/asic/scripts/pnr.tcl → deepsocflow/asic/scripts/pnr.tcl b/asic/scripts/pnr.tcl → deepsocflow/asic/scripts/pnr.tcl
diff --git a/asic/scripts/reportDesign.tcl → deepsocflow/asic/scripts/reportDesign.tcl b/asic/scripts/reportDesign.tcl → deepsocflow/asic/scripts/reportDesign.tcl
diff --git a/asic/scripts/route.tcl → deepsocflow/asic/scripts/route.tcl b/asic/scripts/route.tcl → deepsocflow/asic/scripts/route.tcl
diff --git a/asic/scripts/run_dc.tcl → deepsocflow/asic/scripts/run_dc.tcl b/asic/scripts/run_dc.tcl → deepsocflow/asic/scripts/run_dc.tcl
diff --git a/asic/scripts/run_genus.tcl → deepsocflow/asic/scripts/run_genus.tcl b/asic/scripts/run_genus.tcl → deepsocflow/asic/scripts/run_genus.tcl
diff --git a/asic/scripts/view.tcl → deepsocflow/asic/scripts/view.tcl b/asic/scripts/view.tcl → deepsocflow/asic/scripts/view.tcl
diff --git a/c/example.c → deepsocflow/c/example.c b/c/example.c → deepsocflow/c/example.c
diff --git a/c/runtime.h → deepsocflow/c/runtime.h b/c/runtime.h → deepsocflow/c/runtime.h
@@ -24,7 +24,7 @@ typedef const struct {
 
 typedef enum {POOL_NONE, POOL_MAX, POOL_AVG} Pool_t;
 
-#include "model.h"
+#include "config_fw.h"
 #define X_BITS            (1 << X_BITS_L2)
 #define X_WORDS_PER_BYTE  (8 / X_BITS)
 #define X_BITS_MASK       ((1 << X_BITS) -1)

diff --git a/fpga/scripts/pynq_z2.tcl → deepsocflow/fpga/scripts/pynq_z2.tcl b/fpga/scripts/pynq_z2.tcl → deepsocflow/fpga/scripts/pynq_z2.tcl
diff --git a/fpga/scripts/vivado.tcl → deepsocflow/fpga/scripts/vivado.tcl b/fpga/scripts/vivado.tcl → deepsocflow/fpga/scripts/vivado.tcl
diff --git a/fpga/scripts/zcu104.tcl → deepsocflow/fpga/scripts/zcu104.tcl b/fpga/scripts/zcu104.tcl → deepsocflow/fpga/scripts/zcu104.tcl
diff --git a/deepsocflow/py/__init__.py b/deepsocflow/py/__init__.py
@@ -0,0 +1,3 @@
+from . import hardware, bundle
+from .hardware import *
+from .bundle import *
diff --git a/test/py/bundle.py → deepsocflow/py/bundle.py b/test/py/bundle.py → deepsocflow/py/bundle.py
diff --git a/deepsocflow/py/hardware.py b/deepsocflow/py/hardware.py
@@ -58,8 +58,8 @@ def __init__(
         self.XN_MAX = max_batch_size
         self.CI_MAX = max_channels_in
         self.CO_MAX = max_channels_out
-        self.KH_MAX, self.KW_MAX = max_kernel_size if (type(max_kernel_size) == tuple) else (max_kernel_size, max_kernel_size)
-        self.XH_MAX, self.XW_MAX = max_image_size if (type(max_image_size) == tuple) else (max_image_size, max_image_size)
+        self.KH_MAX, self.KW_MAX = tuple(max_kernel_size) if (type(max_kernel_size) in [tuple, list]) else (max_kernel_size, max_kernel_size)
+        self.XH_MAX, self.XW_MAX = tuple(max_image_size ) if (type(max_image_size ) in [tuple, list]) else (max_image_size , max_image_size )
 
         self.RAM_WEIGHTS_DEPTH     = int((weights_cache_kbytes*1024)/(self.K_BITS*self.COLS*2))
         '''

diff --git a/rtl/axis_out_shift.sv → deepsocflow/rtl/axis_out_shift.sv b/rtl/axis_out_shift.sv → deepsocflow/rtl/axis_out_shift.sv
@@ -1,4 +1,4 @@
-`include "../rtl/include/params.svh"
+`include "defines.svh"
 
 module axis_out_shift #(
   localparam ROWS                 = `ROWS                 ,

diff --git a/rtl/axis_pixels.sv → deepsocflow/rtl/axis_pixels.sv b/rtl/axis_pixels.sv → deepsocflow/rtl/axis_pixels.sv
@@ -1,5 +1,5 @@
 `timescale 1ns/1ps
-`include "../rtl/include/params.svh"
+`include "defines.svh"
 
 module axis_pixels #(
   parameter   ROWS               = `ROWS               ,

diff --git a/rtl/axis_weight_rotator.sv → deepsocflow/rtl/axis_weight_rotator.sv b/rtl/axis_weight_rotator.sv → deepsocflow/rtl/axis_weight_rotator.sv
@@ -3,7 +3,7 @@ Engineer: Abarajithan G.
 Design Name: AXIS Weight Rotator    
 */
 `timescale 1ns/1ps
-`include "../rtl/include/params.svh"
+`include "defines.svh"
 
 module axis_weight_rotator #(
   parameter 

diff --git a/rtl/counter.sv → deepsocflow/rtl/counter.sv b/rtl/counter.sv → deepsocflow/rtl/counter.sv
diff --git a/rtl/sram/cyclic_bram.sv → deepsocflow/rtl/cyclic_bram.sv b/rtl/sram/cyclic_bram.sv → deepsocflow/rtl/cyclic_bram.sv
diff --git a/rtl/include/params.svh → deepsocflow/rtl/defines.svh b/rtl/include/params.svh → deepsocflow/rtl/defines.svh
@@ -1,4 +1,4 @@
-    `include "params_input.svh"
+    `include "config_hw.svh"
 
     `define BITS_KW2  $clog2((`KW_MAX+1)/2)
 

diff --git a/rtl/dnn_engine.v → deepsocflow/rtl/dnn_engine.v b/rtl/dnn_engine.v → deepsocflow/rtl/dnn_engine.v
@@ -1,6 +1,6 @@
 `timescale 1ns/1ps
 `define VERILOG
-`include "../rtl/include/params.svh"
+`include "defines.svh"
 `undef  VERILOG
 
 module dnn_engine #(

diff --git a/rtl/ext/alex_axis_adapter.v → deepsocflow/rtl/ext/alex_axis_adapter.v b/rtl/ext/alex_axis_adapter.v → deepsocflow/rtl/ext/alex_axis_adapter.v
diff --git a/rtl/ext/alex_axis_adapter_any.sv → deepsocflow/rtl/ext/alex_axis_adapter_any.sv b/rtl/ext/alex_axis_adapter_any.sv → deepsocflow/rtl/ext/alex_axis_adapter_any.sv
diff --git a/rtl/ext/alex_axis_pipeline_register.v → ...low/rtl/ext/alex_axis_pipeline_register.v b/rtl/ext/alex_axis_pipeline_register.v → ...low/rtl/ext/alex_axis_pipeline_register.v
diff --git a/rtl/ext/alex_axis_register.v → deepsocflow/rtl/ext/alex_axis_register.v b/rtl/ext/alex_axis_register.v → deepsocflow/rtl/ext/alex_axis_register.v
diff --git a/rtl/huffman_2_decoder.sv → deepsocflow/rtl/huffman_2_decoder.sv b/rtl/huffman_2_decoder.sv → deepsocflow/rtl/huffman_2_decoder.sv
diff --git a/rtl/n_delay.sv → deepsocflow/rtl/n_delay.sv b/rtl/n_delay.sv → deepsocflow/rtl/n_delay.sv
diff --git a/rtl/out_ram_switch.sv → deepsocflow/rtl/out_ram_switch.sv b/rtl/out_ram_switch.sv → deepsocflow/rtl/out_ram_switch.sv
@@ -1,4 +1,4 @@
-`include "../rtl/include/params.svh"
+`include "defines.svh"
 
 module out_ram_switch #(
   localparam ROWS                 = `ROWS   ,

diff --git a/rtl/proc_element.sv → deepsocflow/rtl/proc_element.sv b/rtl/proc_element.sv → deepsocflow/rtl/proc_element.sv
diff --git a/rtl/proc_engine.sv → deepsocflow/rtl/proc_engine.sv b/rtl/proc_engine.sv → deepsocflow/rtl/proc_engine.sv
@@ -1,5 +1,5 @@
 `timescale 1ns/1ps
-`include "../rtl/include/params.svh"
+`include "defines.svh"
 
 module proc_engine #(
   localparam  COLS                = `COLS                ,

diff --git a/test/py/performance.ipynb → deepsocflow/test/py/performance.ipynb b/test/py/performance.ipynb → deepsocflow/test/py/performance.ipynb
diff --git a/test/py/pooling_no_np.ipynb → deepsocflow/test/py/pooling_no_np.ipynb b/test/py/pooling_no_np.ipynb → deepsocflow/test/py/pooling_no_np.ipynb
diff --git a/test/py/resnet18_bundle_api.ipynb → ...socflow/test/py/resnet18_bundle_api.ipynb b/test/py/resnet18_bundle_api.ipynb → ...socflow/test/py/resnet18_bundle_api.ipynb
diff --git a/test/py/resnet50_parser.ipynb → deepsocflow/test/py/resnet50_parser.ipynb b/test/py/resnet50_parser.ipynb → deepsocflow/test/py/resnet50_parser.ipynb
diff --git a/test/py/single_workload_check.ipynb → ...cflow/test/py/single_workload_check.ipynb b/test/py/single_workload_check.ipynb → ...cflow/test/py/single_workload_check.ipynb
diff --git a/test/py/tiling.ipynb → deepsocflow/test/py/tiling.ipynb b/test/py/tiling.ipynb → deepsocflow/test/py/tiling.ipynb
diff --git a/test/sv/axis_tb.sv → deepsocflow/test/sv/axis_tb.sv b/test/sv/axis_tb.sv → deepsocflow/test/sv/axis_tb.sv
diff --git a/test/sv/counter_tb.sv → deepsocflow/test/sv/counter_tb.sv b/test/sv/counter_tb.sv → deepsocflow/test/sv/counter_tb.sv
diff --git a/test/sv/dma.sv → deepsocflow/test/sv/dma.sv b/test/sv/dma.sv → deepsocflow/test/sv/dma.sv
diff --git a/test/sv/dnn_engine_tb.sv → deepsocflow/test/sv/dnn_engine_tb.sv b/test/sv/dnn_engine_tb.sv → deepsocflow/test/sv/dnn_engine_tb.sv
@@ -1,7 +1,7 @@
 `timescale 1ns/1ps
 
-`include "../../rtl/include/params.svh"
-`include "../xsim/sim_params.svh"
+`include "../../rtl/defines.svh"
+`include "config_tb.svh"
 
 module dnn_engine_tb;
 

diff --git a/test/sv/ram_raw.sv → deepsocflow/test/sv/ram_raw.sv b/test/sv/ram_raw.sv → deepsocflow/test/sv/ram_raw.sv
@@ -1,5 +1,5 @@
 `timescale 1ns/1ps
-`include "../../rtl/include/params.svh"
+`include "../../rtl/defines.svh"
 
 module ram_raw #(
   parameter   DEPTH   = 1,

diff --git a/test/sv/skid_buffer_tb.sv → deepsocflow/test/sv/skid_buffer_tb.sv b/test/sv/skid_buffer_tb.sv → deepsocflow/test/sv/skid_buffer_tb.sv
diff --git a/test/wave/dnn_engine_tb_behav.wcfg → ...ocflow/test/wave/dnn_engine_tb_behav.wcfg b/test/wave/dnn_engine_tb_behav.wcfg → ...ocflow/test/wave/dnn_engine_tb_behav.wcfg
diff --git a/pyproject.toml b/pyproject.toml
@@ -4,7 +4,7 @@ build-backend = "flit_core.buildapi"
 
 [project]
 name = "deepsocflow"
-authors = [{name = "Abarajithan G", email = "[email protected]"}]
+authors = [{name = "Abarajithan G", email = "[email protected]"}, {name = "Zhenghua Ma", email = "[email protected]"}]
 version = "0.0.1"
 description = "Your DNNs to FPGA/ASIC SoCs in minutes!"
 requires-python = ">=3.10"

diff --git a/rtl/sram/sdp_array.sv b/rtl/sram/sdp_array.sv
diff --git a/asic/reports/area.rpt → run/asic/reports/area.rpt b/asic/reports/area.rpt → run/asic/reports/area.rpt
diff --git a/asic/reports/power.rpt → run/asic/reports/power.rpt b/asic/reports/power.rpt → run/asic/reports/power.rpt
diff --git a/asic/reports/timing.rpt → run/asic/reports/timing.rpt b/asic/reports/timing.rpt → run/asic/reports/timing.rpt