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...echnerstrukturen/alle-prozesse-haben-bei-mpi-denselben-quellcode-wie-also-ka.md
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# Note | ||
``` | ||
guid: u4X@}L(y!v | ||
notetype: Basic-d7a3e-4ce08 | ||
``` | ||
|
||
### Tags | ||
``` | ||
06_mpi_openmp | ||
``` | ||
|
||
## Front | ||
Alle Prozesse haben bei MPI denselben Quellcode. <div> | ||
</div><div>Wie also kann man bei MPI entscheiden, was welcher Prozess welche Codeteile ausführt?</div> | ||
|
||
## Back | ||
Unterscheidung über <i>process rank</i>.<div><i>process rank</i> wird während Prozessinitialisierung durch System zugeteilt. | ||
</div> |
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...echnerstrukturen/betrachten-sie-nachfolgendes-einfaches-multiprozessorsystem.md
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# Note | ||
``` | ||
guid: IjB%X[/mk< | ||
notetype: Basic-d7a3e-4ce08 | ||
``` | ||
|
||
### Tags | ||
``` | ||
04_koheraenz | ||
11_para_block_prozess | ||
``` | ||
|
||
## Front | ||
Betrachten Sie nachfolgendes einfaches Multiprozessorsystem mit 2 | ||
Prozessoren. | ||
<div> | ||
<div><img src="11071569.png"></div> | ||
</div> | ||
<div> | ||
Ein Pfeil steht für Adressbus, der andere für Datenbus. | ||
</div> | ||
<div> | ||
Rotes Rechteck repräsentiert Speicherblock, der in Caches geholt | ||
wird. | ||
</div> | ||
<div> | ||
Vollziehen Sie nach, welche Zustandsübergänge beim MESI-Protokoll | ||
bei 4 aufeinander folgenden Zugriffen auf ein und denselben | ||
Speicherblock erfolgen? | ||
</div> | ||
|
||
## Back | ||
<img src="28104388.png"> | ||
<div> | ||
2. Prozessor beobachtet, dass Leseoperation durchgeführt wird. | ||
</div> | ||
<div> | ||
Exclusive Read miss liegt vor. Eintrag ist nicht vorhanden. | ||
</div> | ||
<div> | ||
Cachezeile, in die der Block geladen wird, geht vom Zustand | ||
invalid in Zustand exclusive. | ||
</div><img src="81624736.png"> | ||
<div> | ||
Anschließend führen wir ein Lesen auf die Adresse 8 durch. Block | ||
muss aus dem Hauptspeicher geladen werden. | ||
</div> | ||
<div> | ||
Prozessor 1 beobachtet Lesezugriff auf Adresse, die er in seinem | ||
Cache findet (Snoop Hit on a Read). Prozessor schickt shared | ||
Signal. Cachezeile wechselt in den Zustand shared. | ||
</div> | ||
<div><img src="52990270.png"></div> | ||
<div> | ||
Prozessor 1 verändert Wert z. B. 500. Wir ändern Cachezeile von | ||
shared in Zustand modified. | ||
</div> | ||
<div> | ||
Wir schicken dann invalid Signal, anderer Prozessor invalidiert | ||
Block mit dieser Adresse. | ||
</div> | ||
<div><img src="60387747.png"></div> | ||
<div> | ||
Cachezeile ist ungültig. Wir haben Fehlzugriff. Lesezugriff führt | ||
zu Treffer im Cache (Snoop Hit on a Read). Wir schicken dann das | ||
Retry-Signal. Prozessor 2 unterbricht Laden des Blocks aus | ||
Hauptspeicher. | ||
</div> | ||
<div> | ||
Prozessor 1 wechselt in Zustand shared. | ||
</div> | ||
<div> | ||
Das wird wieder von Prozessor 2 beobachtet. Wir haben Snoop-Hit | ||
on a Read. Wir gehen in Zustand shared über. | ||
</div> |
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⚡ Heterogene Rechnerstrukturen/dürfen-in-einem-abgeschwächten-konsisten.md
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...chnerstrukturen/dürfen-in-einem-abgeschwächten-konsistenzmodell-speicherbefe.md
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# Note | ||
``` | ||
guid: id#ySVP#6= | ||
notetype: Basic-d7a3e-4ce08 | ||
``` | ||
|
||
### Tags | ||
``` | ||
04_koheraenz | ||
11_para_block_prozess | ||
``` | ||
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## Front | ||
Dürfen in einem <b>abgeschwächten Konsistenzmodell</b> <b>Speicherbefehle</b> gepuffert werden? Dürfen <b>Synchronisationsbefehle</b> gepuffert werden? | ||
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||
## Back | ||
Puffern von Schreibzugriffen ist erlaubt. Puffern von Synchronisationsbefehlen nicht. |
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⚡ Heterogene Rechnerstrukturen/entspricht-die-anzahl-der-prozesse-der-a.md
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...chnerstrukturen/entspricht-die-anzahl-der-prozesse-der-anzahl-der-prozessore.md
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# Note | ||
``` | ||
guid: Jp_](Rw~al | ||
notetype: Basic-d7a3e-4ce08 | ||
``` | ||
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### Tags | ||
``` | ||
02_vorlesung | ||
``` | ||
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## Front | ||
<p>Entspricht die Anzahl der Prozesse der Anzahl der Prozessoren? | ||
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## Back | ||
Die Anzahl der Prozesse ist <b>nicht</b> zwingend gleich der Anzahl | ||
der Prozessoren. Dies liegt insbesondere an der Virtualisierung von | ||
Multiprozessoren. |
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...ene Rechnerstrukturen/erklären-das-pipelining-am-beispiel-der-vektoraddition.md
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# Note | ||
``` | ||
guid: tp{0.G!qqo | ||
notetype: Basic-d7a3e-4ce08 | ||
``` | ||
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### Tags | ||
``` | ||
het_rs::07_vektorprozessoren | ||
``` | ||
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## Front | ||
Erklären das <b>Pipelining</b> am Beispiel der | ||
<b>Vektoraddition</b>. | ||
|
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## Back | ||
Gleitkommaoperationen sind zu komplex, als dass sie i. d. R. in | ||
einem Taktyzyklus abgearbeitet werden können. | ||
<div> | ||
Deshalb erfolgt eine Aufteilung in mehrere Schritte. | ||
<div><img src= | ||
"paste-e8859c71078380c3e3549ff2f134c1b3aede56cd.jpg"></div> | ||
</div> |
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⚡ Heterogene Rechnerstrukturen/erklären-das-pipelining-am-beispiel-der.md
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