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@xiaoling-yi xiaoling-yi released this 24 Oct 13:29
· 22 commits to main since this release
v0.2.4
b0ae2e3
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What's Changed

  • Add datapath extension broadcaster for the gemm accelerator, add sw support for matmul and conv @xiaoling-yi @IveanEx
  • Modify writer's (but not reader) buffer to normal one instead of pipe one to solve combinational loop @IveanEx
  • AsyncQueue in streamer for Accelerators with slower Clocks @IveanEx @xiaoling-yi
  • Increase spatial dim of C32 and D32 in GeMMX to 2 @xiaoling-yi
  • Remove bender sim targets for SYN and fix vsim preparation @rgantonio
  • Add observable pins per cluster @rgantonio
  • New affine address mapper in AGU for non-interleaved data access and conv sw support @IveanEx @xiaoling-yi
  • Add explicit im2col sw and golden model @xiaoling-yi
  • Fix simd critical path @xiaoling-yi
  • Change Chisel build tool from Mill to sbt @xiaoling-yi
  • Refactor hw cfg to for the HeMAiA integration @IveanEx

Contributors

rgantonio, IveanEx, and xiaoling-yi
Assets 2
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