Add --disable-tracing and --prefix-trace options to snax_cluster

[JosseVanDelm]

This adds two extra options to snitch_cluster, to address #395

This was quite difficult to figure out, the way i've implemented it now is like this:

2 C++ functions that return a command-line value --> DPI-C --> SystemVerilog Tracer

• --disable-tracing : turns off tracing for the Verilog simulation, might speed up some long-taking CI runs, for which we don't care about log parsing anyway...
• --prefix-trace="prefix": appends a prefix to the output traces. If you use this, it will not default to a logs folder anymore, so be sure to include logs/your_prefix in the prefix if you want it to end up in a folder.

I'm keeping this as a draft for now because of the following reasons:

• I don't know how to test this for VCS or Questa (@IveanEx @xiaoling-yi ) can you help me with that? Right now it is implemented in a way that is quite likely to break those latter two, although it should be easily fixable with some preprocessor magic (that would make it impossible to use this functionality on VCS or questa though...)
• The argument parser is really janky... It separately parses the options I added, and then passes this on to the simulator. The reason for this is that the rest of the argument parsing is done by htif.cc from riscv-isa-sim/fesvr... Not sure if we are using any of those arguments right now though...
• @IveanEx has pointed out that there are multiple other places in the systemverilog that write to a separate log file. I would like to detect those and make them happen in a single place... the current way is pretty ugly/impractical...

[JosseVanDelm]

I wanted to concatenate the strings here in systemverilog, but that made the verilator quite angry, so now I'm using this really dumb sformat

[JosseVanDelm]

I changed this to svBit, because verilator seemed to generate a DPI function that expected that... not sure how else I would've figured out...

[JosseVanDelm]

@IveanEx has pointed out that there are multiple other places in the systemverilog that write to a separate log file. I would like to detect those and make them happen in a single place... the current way is pretty ugly/impractical...

@IveanEx the only other place I have found this was already behind an ifndef VERILATOR inside hw/future/src/dma/axi_dma_backend.sv, so I'd mark this problem as solved

[IveanEx]

This PR breaks the HeMAiA's Verilator simulation flow (make hemaia_system_vlt at the root directory). Can you also make a PR to the main branch of HeMAiA to fix it?

Beside this error, other tests with Questa and VCS can pass without problem.

[JosseVanDelm]

This PR breaks the HeMAiA's Verilator simulation flow (make hemaia_system_vlt at the root directory). Can you also make a PR to the main branch of HeMAiA to fix it?

@IveanEx
PR is ready at: KULeuven-MICAS/HeMAiA#90