tpl: update cluster wrapper

KULeuven-MICAS · Jul 13, 2024 · 9276070 · 9276070
1 parent cecb0c8
commit 9276070
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl b/hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl
@@ -352,7 +352,6 @@ module ${cfg['name']}_wrapper (
   // Convert input port
   // From AXI port to cluster 
   axi_dw_converter #(
-    .AxiMaxReads         ( ${cfg['wide_trans']}                       ), // Number of outstanding reads
     .AxiSlvPortDataWidth ( ${cfg['pkg_name']}::LowBWWideDataWidth     ), // Data width of the slv port
     .AxiMstPortDataWidth ( ${cfg['pkg_name']}::WideDataWidth          ), // Data width of the mst port
     .AxiAddrWidth        ( ${cfg['pkg_name']}::AddrWidth              ), // Address width
@@ -382,7 +381,6 @@ module ${cfg['name']}_wrapper (
   // Convert output ports
   // From cluster to AXI port
   axi_dw_converter #(
-    .AxiMaxReads         ( ${cfg['wide_trans']}                         ), // Number of outstanding reads
     .AxiSlvPortDataWidth ( ${cfg['pkg_name']}::WideDataWidth            ), // Data width of the slv port
     .AxiMstPortDataWidth ( ${cfg['pkg_name']}::LowBWWideDataWidth       ), // Data width of the mst port
     .AxiAddrWidth        ( ${cfg['pkg_name']}::AddrWidth                ), // Address width
@@ -408,6 +406,7 @@ module ${cfg['name']}_wrapper (
     .mst_req_o           ( wide_out_req_o  ),
     .mst_resp_i          ( wide_out_resp_i )
   );
+
 % endif
 
 <%