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Move memories into modules for PNR power routing (#198)
* bender: add new module files to bender * hw: add new moduled icaches * hw: use updated module caches * hw: take out comments * bender: add data mem sv * hw: use data mem sv * hw: add data memory
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,54 @@ | ||
| // Copyright 2024 KU Leuven. | ||
| // Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| // SPDX-License-Identifier: SHL-0.51 | ||
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| // Ryan Antonio <[email protected]> | ||
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| // The actual data memory. This memory is made into a module | ||
| // to support multiple power domain needed by the floor plan tool | ||
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| module snitch_data_mem #( | ||
| parameter int unsigned TCDMDepth = 1024, | ||
| parameter int unsigned NarrowDataWidth = 64, | ||
| parameter int unsigned NumTotalBanks = 32, | ||
| // Memory configuration input types; these vary depending on implementation. | ||
| parameter type sram_cfg_t = logic, | ||
| parameter type sram_cfgs_t = logic, | ||
| parameter type tcdm_mem_addr_t = logic, | ||
| parameter type strb_t = logic, | ||
| parameter type data_t = logic | ||
| )( | ||
| input logic clk_i, | ||
| input logic rst_ni, | ||
| input sram_cfgs_t sram_cfgs_i, | ||
| input logic [NumTotalBanks-1:0] mem_cs_i, | ||
| input tcdm_mem_addr_t [NumTotalBanks-1:0] mem_add_i, | ||
| input logic [NumTotalBanks-1:0] mem_wen_i, | ||
| input strb_t [NumTotalBanks-1:0] mem_be_i, | ||
| input data_t [NumTotalBanks-1:0] mem_wdata_i, | ||
| output data_t [NumTotalBanks-1:0] mem_rdata_o | ||
| ); | ||
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| for (genvar i = 0; i < NumTotalBanks; i++) begin: gen_banks | ||
| tc_sram_impl #( | ||
| .NumWords ( TCDMDepth ), | ||
| .DataWidth ( NarrowDataWidth ), | ||
| .ByteWidth ( 8 ), | ||
| .NumPorts ( 1 ), | ||
| .Latency ( 1 ), | ||
| .impl_in_t ( sram_cfg_t ) | ||
| ) i_data_mem ( | ||
| .clk_i ( clk_i ), | ||
| .rst_ni ( rst_ni ), | ||
| .impl_i ( sram_cfgs_i.tcdm ), | ||
| .impl_o ( /*Unused*/ ), | ||
| .req_i ( mem_cs_i[i] ), | ||
| .we_i ( mem_wen_i[i] ), | ||
| .addr_i ( mem_add_i[i] ), | ||
| .be_i ( mem_be_i[i] ), | ||
| .wdata_i ( mem_wdata_i[i] ), | ||
| .rdata_o ( mem_rdata_o[i] ) | ||
| ); | ||
| end | ||
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| endmodule |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,47 @@ | ||
| // Copyright 2024 KU Leuven. | ||
| // Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| // SPDX-License-Identifier: SHL-0.51 | ||
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| // Ryan Antonio <[email protected]> | ||
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| // The actual cache memory. This memory is made into a module | ||
| // to support multiple power domain needed by the floor plan tool | ||
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| module snitch_icache_data #( | ||
| parameter snitch_icache_pkg::config_t CFG = '0, | ||
| /// Configuration input types for SRAMs used in implementation. | ||
| parameter type sram_cfg_data_t = logic | ||
| )( | ||
| input logic clk_i, | ||
| input logic rst_ni, | ||
| input sram_cfg_data_t sram_cfg_data_i, | ||
| input logic [ CFG.SET_COUNT-1:0] ram_enable_i, | ||
| input logic ram_write_i, | ||
| input logic [CFG.COUNT_ALIGN-1:0] ram_addr_i, | ||
| input logic [ CFG.SET_COUNT-1:0][CFG.LINE_WIDTH-1:0] ram_wdata_i, | ||
| output logic [ CFG.SET_COUNT-1:0][CFG.LINE_WIDTH-1:0] ram_rdata_o | ||
| ); | ||
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| for (genvar i = 0; i < CFG.SET_COUNT; i++) begin: g_cache_data_sets | ||
| tc_sram_impl #( | ||
| .NumWords ( CFG.LINE_COUNT ), | ||
| .DataWidth ( CFG.LINE_WIDTH ), | ||
| .ByteWidth ( 8 ), | ||
| .NumPorts ( 1 ), | ||
| .Latency ( 1 ), | ||
| .impl_in_t ( sram_cfg_data_t ) | ||
| ) i_data ( | ||
| .clk_i ( clk_i ), | ||
| .rst_ni ( rst_ni ), | ||
| .impl_i ( sram_cfg_data_i ), | ||
| .impl_o ( /*Unused*/ ), | ||
| .req_i ( ram_enable_i[i] ), | ||
| .we_i ( ram_write_i ), | ||
| .addr_i ( ram_addr_i ), | ||
| .wdata_i ( ram_wdata_i ), | ||
| .be_i ( '1 ), | ||
| .rdata_o ( ram_rdata_o[i] ) | ||
| ); | ||
| end | ||
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| endmodule |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,47 @@ | ||
| // Copyright 2024 KU Leuven. | ||
| // Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| // SPDX-License-Identifier: SHL-0.51 | ||
|
|
||
| // Ryan Antonio <[email protected]> | ||
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| // The actual cache tag memory. This memory is made into a module | ||
| // to support multiple power domain needed by the floor plan tool | ||
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| module snitch_icache_tag #( | ||
| parameter snitch_icache_pkg::config_t CFG = '0, | ||
| /// Configuration input types for SRAMs used in implementation. | ||
| parameter type sram_cfg_tag_t = logic | ||
| )( | ||
| input logic clk_i, | ||
| input logic rst_ni, | ||
| input sram_cfg_tag_t sram_cfg_tag_i, | ||
| input logic [ CFG.SET_COUNT-1:0] ram_enable_i, | ||
| input logic ram_write_i, | ||
| input logic [CFG.COUNT_ALIGN-1:0] ram_addr_i, | ||
| input logic [ CFG.SET_COUNT-1:0][CFG.TAG_WIDTH+1:0] ram_wtag_i, | ||
| output logic [ CFG.SET_COUNT-1:0][CFG.TAG_WIDTH+1:0] ram_rtag_o | ||
| ); | ||
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| for (genvar i = 0; i < CFG.SET_COUNT; i++) begin: g_cache_tag_sets | ||
| tc_sram_impl #( | ||
| .NumWords ( CFG.LINE_COUNT ), | ||
| .DataWidth ( CFG.TAG_WIDTH+2 ), | ||
| .ByteWidth ( 8 ), | ||
| .NumPorts ( 1 ), | ||
| .Latency ( 1 ), | ||
| .impl_in_t ( sram_cfg_tag_t ) | ||
| ) i_tag ( | ||
| .clk_i ( clk_i ), | ||
| .rst_ni ( rst_ni ), | ||
| .impl_i ( sram_cfg_tag_i ), | ||
| .impl_o ( /*Unused*/ ), | ||
| .req_i ( ram_enable_i[i] ), | ||
| .we_i ( ram_write_i ), | ||
| .addr_i ( ram_addr_i ), | ||
| .wdata_i ( ram_wtag_i ), | ||
| .be_i ( '1 ), | ||
| .rdata_o ( ram_rtag_o[i] ) | ||
| ); | ||
| end | ||
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| endmodule |