xdma autogen C header (#201)

* Remove the header from the git repo as it will be automatically generated

* Auto generation of C header in Chisel

* Reformat wrappergen

* Remove the gitignore so that compilation of sw can pass  for the case with no integration of xdma

* Reformat C header

hw/chisel/src/main/scala/snax/xdma/xdmaTop/xdmaTop.scala

@@ -193,22 +193,73 @@ object xdmaTopGen extends App {
       parsed_args("axiDataWidth").toInt / parsed_args("tcdmDataWidth").toInt,
     addressBufferDepth = parsed_args("writerBufferDepth").toInt
   )
-
-  var extensionparam = Seq[HasDMAExtension]()
+  var readerextensionparam = Seq[HasDMAExtension]()
+  var writerextensionparam = Seq[HasDMAExtension]()
   if (parsed_args.contains("HasMemset"))
-    extensionparam = extensionparam :+ HasMemset
+    writerextensionparam = writerextensionparam :+ HasMemset
   if (parsed_args.contains("HasMaxPool"))
-    extensionparam = extensionparam :+ HasMaxPool
+    writerextensionparam = writerextensionparam :+ HasMaxPool
   if (parsed_args.contains("HasTransposer"))
-    extensionparam = extensionparam :+ HasTransposer
+    writerextensionparam = writerextensionparam :+ HasTransposer
 
+  // Generation of the hardware
   emitVerilog(
     new xdmaTop(
       clusterName = parsed_args.getOrElse("clusterName", ""),
-      readerparam = new DMADataPathParam(readerparam, Seq()),
-      writerparam = new DMADataPathParam(writerparam, extensionparam)
+      readerparam = new DMADataPathParam(readerparam, readerextensionparam),
+      writerparam = new DMADataPathParam(writerparam, writerextensionparam)
     ),
     args =
-      Array("--target-dir", parsed_args.getOrElse("target-dir", "generated"))
+      Array("--target-dir", parsed_args.getOrElse("hw-target-dir", "generated"))
+  )
+
+  // Generation of the software #define macros
+  val macro_dir = parsed_args.getOrElse(
+    "sw-target-dir",
+    "generated"
+  ) + "/include/snax-xdma-csr-addr.h"
+
+  val macro_template =
+    s"""// Copyright 2024 KU Leuven.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Yunhao Deng <[email protected]>
+
+// This file is generated by Chisel in hw/chisel, do not modify it manually
+
+#define XDMA_BASE_ADDR 960
+#define XDMA_SRC_ADDR_PTR_LSB XDMA_BASE_ADDR
+#define XDMA_SRC_ADDR_PTR_MSB XDMA_SRC_ADDR_PTR_LSB + 1
+#define XDMA_SRC_DIM ${readerparam.agu_param.dimension}
+#define XDMA_SRC_BOUND_PTR XDMA_SRC_ADDR_PTR_MSB + 1
+#define XDMA_SRC_STRIDE_PTR XDMA_SRC_BOUND_PTR + XDMA_SRC_DIM
+#define XDMA_SRC_EXT_CSR_PTR XDMA_SRC_STRIDE_PTR + XDMA_SRC_DIM
+#define XDMA_SRC_EXT_NUM ${readerextensionparam.length}
+#define XDMA_SRC_EXT_CSR_NUM ${readerextensionparam
+        .map(_.extensionParam.userCsrNum)
+        .sum + readerextensionparam.length}
+#define XDMA_SRC_EXT_CUSTOM_CSR_NUM \\
+    { ${readerextensionparam.map(_.extensionParam.userCsrNum).mkString(", ")} }
+#define XDMA_DST_ADDR_PTR_LSB XDMA_SRC_EXT_CSR_PTR + XDMA_SRC_EXT_CSR_NUM
+#define XDMA_DST_ADDR_PTR_MSB XDMA_DST_ADDR_PTR_LSB + 1
+#define XDMA_DST_DIM ${writerparam.agu_param.dimension}
+#define XDMA_DST_BOUND_PTR XDMA_DST_ADDR_PTR_MSB + 1
+#define XDMA_DST_STRIDE_PTR XDMA_DST_BOUND_PTR + XDMA_DST_DIM
+#define XDMA_DST_EXT_CSR_PTR XDMA_DST_STRIDE_PTR + XDMA_DST_DIM
+#define XDMA_DST_EXT_NUM ${writerextensionparam.length}
+#define XDMA_DST_EXT_CSR_NUM ${writerextensionparam
+        .map(_.extensionParam.userCsrNum)
+        .sum + writerextensionparam.length}
+#define XDMA_DST_EXT_CUSTOM_CSR_NUM \\
+    { ${writerextensionparam.map(_.extensionParam.userCsrNum).mkString(", ")} }
+#define XDMA_START_PTR XDMA_DST_EXT_CSR_PTR + XDMA_DST_EXT_CSR_NUM
+#define XDMA_COMMIT_TASK_PTR XDMA_START_PTR + 1
+#define XDMA_FINISH_TASK_PTR XDMA_COMMIT_TASK_PTR + 1
+"""
+
+  java.nio.file.Files.write(
+    java.nio.file.Paths.get(macro_dir),
+    macro_template.getBytes(java.nio.charset.StandardCharsets.UTF_8)
   )
 }

target/snitch_cluster/sw/snax/xdma/include/snax-xdma-csr-addr.h

@@ -4,7 +4,7 @@
 //
 // Yunhao Deng <[email protected]>
 
-// This file is (will be) generated by scala, do not modify it manually
+// This file is generated by Chisel in hw/chisel, do not modify it manually
 
 #define XDMA_BASE_ADDR 960
 #define XDMA_SRC_ADDR_PTR_LSB XDMA_BASE_ADDR

util/wrappergen/wrappergen.py

@@ -341,8 +341,9 @@ def main():
             (" --HasMemset " if snax_xdma_cfg["has_memset"] else "") +
             (" --HasMaxPool " if snax_xdma_cfg["has_maxpool"] else "") +
             (" --HasTransposer " if snax_xdma_cfg["has_transposer"] else "") +
-            " --target-dir " + args.gen_path +
-            cfg["cluster"]["name"] + "_xdma/"
+            " --hw-target-dir " + args.gen_path +
+            cfg["cluster"]["name"] + "_xdma/" +
+            " --sw-target-dir " + args.gen_path + "../sw/snax/xdma"
         )
 
     # Generation of testharness