[WIP] Adding pipe registers within Snitch data path #1715
lint.yml
on: pull_request
Lint Verilog sources
44s
Check bender vendor up-to-date
14s
Check Opcodes Up-to-Date
5s
Check License headers
5s
Lint YAML Sources
6s
Lint Python Sources
6s
Lint C/C++ Sources
11s
Lint Editorconfig
4s
Matrix: Lint Scala Files
Annotations
10 warnings
Artifacts
Produced during runtime
Name | Size | |
---|---|---|
verible-linter
Expired
|
164 Bytes |
|