Update the boot addr control

[Konste11ation]

This PR updates the switching logic of the boot addr.

The previous solution works well on simulation and FPGA. However, when I performed the post-synthesis simulation, I found the boot addr is synthesized as follows

occamy_soc i_occamy_soc ( .clk_i(clk_i), .rst_ni(n18135), .test_mode_i(
net24681027), .boot_addr_i({net24681028, net24681029, net24681030,
net24681031, net24681032, net24681033, net24681034, net24681035,
net24681036, net24681037, net24681038, net24681039, net24681040,
net24681041, net24681042, net24681043, boot_addr[31], net24681044,
net24681045, net24681046, net24681047, net24681048, net24681049,
boot_addr[24], net24681050, net24681051, net24681052, net24681053,
net24681054, net24681055, net24681056, net24681057, net24681058,
net24681059, net24681060, net24681061, net24681062, net24681063,
net24681064, net24681065, net24681066, net24681067, net24681068,
net24681069, net24681070, net24681071, net24681072, net24681073}),

Only boot_addr[31] and boot_addr[24] are implemented as DFFs and other bits are just wires.

I have modified the switching logic of the boot addr. Now there are two regs hold the 0x0100_000 and 0x8000_0000 respectively. The external boot_mode_i pin will select from those regs.

I am still waiting for the new synthesis results. If the problem solved, I will push to the chip_antwerp and the main.