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This PR introduces the new SPI Slave for HeMAiA chip, with the accompanying testbench to simulate the read and write behavior.
The SPI slave can be included / excluded by modifying the occamy_cfg files. By removing it from the peripherals, it will be automatically deleted in the generated SystemVerilog files.
To avoid the complexity, I only enable for Questasim simulation environment, and you can uncomment either read / write in testharness.sv (they are uncommented as the speed is quite slow) to see what will happened 😂😂
I tested for the condition by loading one sw, and after a while, I replace this software by injecting new data through SPI. The behavioral test indicates the function meets the expectation. The two tasks will be the golden reference for the later tests of the real chips.