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SPI Slave #57

Merged
merged 10 commits into from
Oct 8, 2024
Merged

SPI Slave #57

merged 10 commits into from
Oct 8, 2024

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IveanEx
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@IveanEx IveanEx commented Oct 7, 2024

This PR introduces the new SPI Slave for HeMAiA chip, with the accompanying testbench to simulate the read and write behavior.

The SPI slave can be included / excluded by modifying the occamy_cfg files. By removing it from the peripherals, it will be automatically deleted in the generated SystemVerilog files.

To avoid the complexity, I only enable for Questasim simulation environment, and you can uncomment either read / write in testharness.sv (they are uncommented as the speed is quite slow) to see what will happened 😂😂

I tested for the condition by loading one sw, and after a while, I replace this software by injecting new data through SPI. The behavioral test indicates the function meets the expectation. The two tasks will be the golden reference for the later tests of the real chips.

@IveanEx IveanEx merged commit 37db678 into chip_antwerp Oct 8, 2024
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@IveanEx IveanEx deleted the ydeng/axiSlave branch October 8, 2024 13:20
IveanEx added a commit that referenced this pull request Nov 2, 2024
* Update occamygen for correct axi slave port generation

* Update occamy_top.sv.tpl

* Bug Fix

* Modify top level IO definition

* Testbench for SPI read

* Bug Fix

* Testbench for SPI write

* Bug Fix

* Bug Fix

* New FPGA Script for SPI Slave
@IveanEx IveanEx mentioned this pull request Nov 2, 2024
IveanEx added a commit that referenced this pull request Nov 2, 2024
* Update occamygen for correct axi slave port generation

* Update occamy_top.sv.tpl

* Bug Fix

* Modify top level IO definition

* Testbench for SPI read

* Bug Fix

* Testbench for SPI write

* Bug Fix

* Bug Fix

* New FPGA Script for SPI Slave
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2 participants