Merge VPK180 and VCU128 FPGA deployment flow

target/fpga/.gitignore

@@ -4,6 +4,7 @@ vivado_ips/xgui
 .Xil/
 xgui/
 define_defines_includes_no_simset.tcl
+probes.ltx
 *.jou
 *.log
 *.zip

target/fpga_chip/hemaia_system/.gitignore

@@ -1,3 +1,3 @@
 /hemaia_system
-/hemaia_system_vcu128
 /define_defines_includes_no_simset.tcl
+/probes.ltx

target/fpga_chip/hemaia_system/Makefile

@@ -34,6 +34,6 @@ define_defines_includes_no_simset.tcl:
 	${BENDER} script vivado $(BENDER_TARGETS) --only-defines --only-includes --no-simset > $@
 
 clean:
-	rm -rf .Xil hemaia_system_vcu128 *.jou *.log *.str define_defines_includes_no_simset.tcl
+	rm -rf .Xil hemaia_system *.jou *.log *.str define_defines_includes_no_simset.tcl
 
 .PHONY: program flash clean

target/fpga_chip/hemaia_system/hemaia_system_vcu128.tcl

@@ -15,7 +15,7 @@ if {$argc > 1 && [lindex $argv 1]} { set EXT_JTAG true }
 set nproc [exec nproc]
 
 # Create project
-set project hemaia_system_vcu128
+set project hemaia_system
 
 create_project $project ./$project -force -part xcvu37p-fsvh2892-2L-e
 set_property board_part xilinx.com:vcu128:part0:1.0 [current_project]
@@ -30,31 +30,31 @@ source hemaia_system_vcu128_bd.tcl
 # Add constraint files
 add_files -fileset constrs_1 -norecurse hemaia_system_vcu128_impl.xdc
 import_files -fileset constrs_1 hemaia_system_vcu128_impl.xdc
-set_property used_in_synthesis false [get_files hemaia_system_vcu128/hemaia_system_vcu128.srcs/constrs_1/imports/hemaia_system/hemaia_system_vcu128_impl.xdc]
+set_property used_in_synthesis false [get_files hemaia_system/hemaia_system.srcs/constrs_1/imports/hemaia_system/hemaia_system_vcu128_impl.xdc]
 if { $EXT_JTAG } {
     add_files -fileset constrs_1 -norecurse hemaia_system_vcu128_impl_ext_jtag.xdc
     import_files -fileset constrs_1 hemaia_system_vcu128_impl_ext_jtag.xdc
-    set_property used_in_synthesis false [get_files hemaia_system_vcu128/hemaia_system_vcu128.srcs/constrs_1/imports/hemaia_system/hemaia_system_vcu128_impl.xdc]
+    set_property used_in_synthesis false [get_files hemaia_system/hemaia_system.srcs/constrs_1/imports/hemaia_system/hemaia_system_vcu128_impl.xdc]
 } else {
     delete_bd_objs [get_bd_nets -of_objects [get_bd_ports "jtag_tck_i jtag_tdi_i jtag_tdo_o jtag_tms_i" ]]
     delete_bd_objs [get_bd_ports jtag_*]
 }
 
 # Generate wrapper
-make_wrapper -files [get_files ./hemaia_system_vcu128/hemaia_system_vcu128.srcs/sources_1/bd/hemaia_system_vcu128/hemaia_system_vcu128.bd] -top
-add_files -norecurse ./hemaia_system_vcu128/hemaia_system_vcu128.gen/sources_1/bd/hemaia_system_vcu128/hdl/hemaia_system_vcu128_wrapper.v
+make_wrapper -files [get_files ./hemaia_system/hemaia_system.srcs/sources_1/bd/hemaia_system/hemaia_system.bd] -top
+add_files -norecurse ./hemaia_system/hemaia_system.gen/sources_1/bd/hemaia_system/hdl/hemaia_system_wrapper.v
 update_compile_order -fileset sources_1
 
 # Create runs
-generate_target all [get_files ./hemaia_system_vcu128/hemaia_system_vcu128.srcs/sources_1/bd/hemaia_system_vcu128/hemaia_system_vcu128.bd]
-export_ip_user_files -of_objects [get_files ./hemaia_system_vcu128/hemaia_system_vcu128.srcs/sources_1/bd/hemaia_system_vcu128/hemaia_system_vcu128.bd] -no_script -sync -force -quiet
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./hemaia_system_vcu128/hemaia_system_vcu128.srcs/sources_1/bd/hemaia_system_vcu128/hemaia_system_vcu128.bd]
+generate_target all [get_files ./hemaia_system/hemaia_system.srcs/sources_1/bd/hemaia_system/hemaia_system.bd]
+export_ip_user_files -of_objects [get_files ./hemaia_system/hemaia_system.srcs/sources_1/bd/hemaia_system/hemaia_system.bd] -no_script -sync -force -quiet
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./hemaia_system/hemaia_system.srcs/sources_1/bd/hemaia_system/hemaia_system.bd]
 
 # Re-add hemaia chip includes
-set build hemaia_system_vcu128
+set build hemaia_system
 
 export_ip_user_files -of_objects [get_ips occamy_chip_0] -no_script -sync -force -quiet
-eval [exec sed {s/current_fileset/get_filesets hemaia_system_vcu128_occamy_chip_0_0/} define_defines_includes_no_simset.tcl]
+eval [exec sed {s/current_fileset/get_filesets hemaia_system_occamy_chip_0/} define_defines_includes_no_simset.tcl]
 
 # Do NOT insert BUFGs on high-fanout nets (e.g. reset). This will backfire during placement.
 set_param logicopt.enableBUFGinsertHFN no
@@ -117,7 +117,7 @@ if ($DEBUG) {
 
     ## Clock
     set_property port_width 1 [get_debug_ports u_ila_0/clk]
-    connect_debug_port u_ila_0/clk [get_nets [list hemaia_system_vcu128_i/clk_wiz/inst/clk_core]]
+    connect_debug_port u_ila_0/clk [get_nets [list hemaia_system_i/clk_wiz/inst/clk_core]]
 
     set debugNets [lsort -dictionary [get_nets -hier -filter {MARK_DEBUG == 1}]]
     set netNameLast ""
@@ -145,9 +145,9 @@ if ($DEBUG) {
         set netNameLast $netName
     }
 
-    set_property target_constrs_file hemaia_system_vcu128/hemaia_system_vcu128.srcs/constrs_1/imports/hemaia_system/hemaia_system_vcu128_impl.xdc [current_fileset -constrset]
+    set_property target_constrs_file hemaia_system/hemaia_system.srcs/constrs_1/imports/hemaia_system/hemaia_system_vcu128_impl.xdc [current_fileset -constrset]
     if { $EXT_JTAG } {
-        set_property target_constrs_file hemaia_system_vcu128/hemaia_system_vcu128.srcs/constrs_1/imports/hemaia_system/hemaia_system_vcu128_impl_ext_jtag.xdc [current_fileset -constrset]
+        set_property target_constrs_file hemaia_system/hemaia_system.srcs/constrs_1/imports/hemaia_system/hemaia_system_vcu128_impl_ext_jtag.xdc [current_fileset -constrset]
     }
     save_constraints -force
 

target/fpga_chip/hemaia_system/hemaia_system_vcu128_bd.tcl

@@ -1,6 +1,6 @@
 
 ################################################################
-# This is a generated script based on design: hemaia_system_vcu128
+# This is a generated script based on design: hemaia_system
 #
 # Though there are limitations about the generated script,
 # the main purpose of this utility is to make learning
@@ -41,7 +41,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
 ################################################################
 
 # To test this script, run the following commands from Vivado Tcl console:
-# source hemaia_system_vcu128_script.tcl
+# source hemaia_system_script.tcl
 
 # If there is no project opened, this script will create a
 # project, but make sure you do not have an existing project
@@ -56,7 +56,7 @@ if { $list_projs eq "" } {
 
 # CHANGE DESIGN NAME HERE
 variable design_name
-set design_name hemaia_system_vcu128
+set design_name hemaia_system
 
 # If you do not already have an existing IP Integrator design open,
 # you can create a design using the following command:
@@ -319,46 +319,46 @@ proc create_root_design { parentCell } {
   set_property CONFIG.DIN_FROM {7} $xlslice_1
 
 
-  # Create instance: occamy_chip_0, and set properties
-  set occamy_chip_0 [ create_bd_cell -type ip -vlnv MICAS_KUL:user:occamy_chip:1.0 occamy_chip_0 ]
+  # Create instance: occamy_chip, and set properties
+  set occamy_chip [ create_bd_cell -type ip -vlnv MICAS_KUL:user:occamy_chip:1.0 occamy_chip ]
 
   # Create interface connections
   connect_bd_intf_net -intf_net default_100mhz_clk_1 [get_bd_intf_ports default_100mhz_clk] [get_bd_intf_pins clk_wiz/CLK_IN1_D]
 
   # Create port connections
-  connect_bd_net -net Net [get_bd_ports spim_sd_io] [get_bd_pins occamy_chip_0/spim_sd_io]
-  connect_bd_net -net Net1 [get_bd_ports i2c_sda_io] [get_bd_pins occamy_chip_0/i2c_sda_io]
+  connect_bd_net -net Net [get_bd_ports spim_sd_io] [get_bd_pins occamy_chip/spim_sd_io]
+  connect_bd_net -net Net1 [get_bd_ports i2c_sda_io] [get_bd_pins occamy_chip/i2c_sda_io]
   set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets Net1]
-  connect_bd_net -net Net2 [get_bd_ports i2c_scl_io] [get_bd_pins occamy_chip_0/i2c_scl_io]
+  connect_bd_net -net Net2 [get_bd_ports i2c_scl_io] [get_bd_pins occamy_chip/i2c_scl_io]
   set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets Net2]
-  connect_bd_net -net c_high_dout [get_bd_pins c_high/dout] [get_bd_ports jtag_vdd_o] [get_bd_pins occamy_chip_0/jtag_trst_ni]
-  connect_bd_net -net clk_wiz_clk_core [get_bd_pins clk_wiz/clk_core] [get_bd_pins vio_sys/clk] [get_bd_pins occamy_chip_0/clk_i] [get_bd_pins occamy_chip_0/clk_periph_i]
-  connect_bd_net -net clk_wiz_clk_rtc [get_bd_pins clk_wiz/clk_rtc] [get_bd_pins occamy_chip_0/rtc_i]
-  connect_bd_net -net const_low_dout [get_bd_pins c_low/dout] [get_bd_ports jtag_gnd_o] [get_bd_pins occamy_chip_0/test_mode_i] [get_bd_pins occamy_chip_0/gpio_d_i] [get_bd_pins occamy_chip_0/ext_irq_i]
-  connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins occamy_chip_0/jtag_tck_i]
+  connect_bd_net -net c_high_dout [get_bd_pins c_high/dout] [get_bd_ports jtag_vdd_o] [get_bd_pins occamy_chip/jtag_trst_ni]
+  connect_bd_net -net clk_wiz_clk_core [get_bd_pins clk_wiz/clk_core] [get_bd_pins vio_sys/clk] [get_bd_pins occamy_chip/clk_i] [get_bd_pins occamy_chip/clk_periph_i]
+  connect_bd_net -net clk_wiz_clk_rtc [get_bd_pins clk_wiz/clk_rtc] [get_bd_pins occamy_chip/rtc_i]
+  connect_bd_net -net const_low_dout [get_bd_pins c_low/dout] [get_bd_ports jtag_gnd_o] [get_bd_pins occamy_chip/test_mode_i] [get_bd_pins occamy_chip/gpio_d_i] [get_bd_pins occamy_chip/ext_irq_i]
+  connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins occamy_chip/jtag_tck_i]
   set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets jtag_tck_i_1]
-  connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins occamy_chip_0/jtag_tdi_i]
+  connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins occamy_chip/jtag_tdi_i]
   set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets jtag_tdi_i_1]
-  connect_bd_net -net jtag_tms_i_1 [get_bd_ports jtag_tms_i] [get_bd_pins occamy_chip_0/jtag_tms_i]
+  connect_bd_net -net jtag_tms_i_1 [get_bd_ports jtag_tms_i] [get_bd_pins occamy_chip/jtag_tms_i]
   set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets jtag_tms_i_1]
-  connect_bd_net -net occamy_chip_0_gpio_d_o [get_bd_pins occamy_chip_0/gpio_d_o] [get_bd_pins xlslice_1/Din]
-  connect_bd_net -net occamy_chip_0_jtag_tdo_o [get_bd_pins occamy_chip_0/jtag_tdo_o] [get_bd_ports jtag_tdo_o]
+  connect_bd_net -net occamy_chip_0_gpio_d_o [get_bd_pins occamy_chip/gpio_d_o] [get_bd_pins xlslice_1/Din]
+  connect_bd_net -net occamy_chip_0_jtag_tdo_o [get_bd_pins occamy_chip/jtag_tdo_o] [get_bd_ports jtag_tdo_o]
   set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_jtag_tdo_o]
-  connect_bd_net -net occamy_chip_0_spim_csb_o [get_bd_pins occamy_chip_0/spim_csb_o] [get_bd_ports spim_csb_o]
-  connect_bd_net -net occamy_chip_0_spim_sck_o [get_bd_pins occamy_chip_0/spim_sck_o] [get_bd_ports spim_sck_o]
-  connect_bd_net -net occamy_chip_0_uart_rts_no [get_bd_pins occamy_chip_0/uart_rts_no] [get_bd_ports uart_rts_no_0]
+  connect_bd_net -net occamy_chip_0_spim_csb_o [get_bd_pins occamy_chip/spim_csb_o] [get_bd_ports spim_csb_o]
+  connect_bd_net -net occamy_chip_0_spim_sck_o [get_bd_pins occamy_chip/spim_sck_o] [get_bd_ports spim_sck_o]
+  connect_bd_net -net occamy_chip_0_uart_rts_no [get_bd_pins occamy_chip/uart_rts_no] [get_bd_ports uart_rts_no_0]
   set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_uart_rts_no]
-  connect_bd_net -net occamy_chip_0_uart_tx_o [get_bd_pins occamy_chip_0/uart_tx_o] [get_bd_ports uart_tx_o_0]
+  connect_bd_net -net occamy_chip_0_uart_tx_o [get_bd_pins occamy_chip/uart_tx_o] [get_bd_ports uart_tx_o_0]
   set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_uart_tx_o]
   connect_bd_net -net occamy_rst [get_bd_pins rst_or_core/Res] [get_bd_pins rst_core_inv/Op1]
   connect_bd_net -net occamy_rst_vio [get_bd_pins vio_sys/probe_out0] [get_bd_pins concat_rst_core/In1]
-  connect_bd_net -net occamy_rstn [get_bd_pins rst_core_inv/Res] [get_bd_pins occamy_chip_0/rst_ni] [get_bd_pins occamy_chip_0/rst_periph_ni]
+  connect_bd_net -net occamy_rstn [get_bd_pins rst_core_inv/Res] [get_bd_pins occamy_chip/rst_ni] [get_bd_pins occamy_chip/rst_periph_ni]
   connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins concat_rst_core/In0]
-  connect_bd_net -net uart_cts_ni_0_1 [get_bd_ports uart_cts_ni_0] [get_bd_pins occamy_chip_0/uart_cts_ni]
+  connect_bd_net -net uart_cts_ni_0_1 [get_bd_ports uart_cts_ni_0] [get_bd_pins occamy_chip/uart_cts_ni]
   set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets uart_cts_ni_0_1]
-  connect_bd_net -net uart_rx_i_0_1 [get_bd_ports uart_rx_i_0] [get_bd_pins occamy_chip_0/uart_rx_i]
+  connect_bd_net -net uart_rx_i_0_1 [get_bd_ports uart_rx_i_0] [get_bd_pins occamy_chip/uart_rx_i]
   set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets uart_rx_i_0_1]
-  connect_bd_net -net vio_sys_probe_out1 [get_bd_pins vio_sys/probe_out1] [get_bd_pins occamy_chip_0/boot_mode_i]
+  connect_bd_net -net vio_sys_probe_out1 [get_bd_pins vio_sys/probe_out1] [get_bd_pins occamy_chip/boot_mode_i]
   connect_bd_net -net xlconcat_2_dout [get_bd_pins concat_rst_core/dout] [get_bd_pins rst_or_core/Op1]
   connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_ports gpio_d_o]
 

target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl.xdc

@@ -74,7 +74,7 @@ set_property PACKAGE_PIN BM29 [get_ports reset]
 set_property IOSTANDARD LVCMOS12 [get_ports reset]
 
 # Set RTC as false path
-set_false_path -to [get_pins occamy_vcu128_i/occamy/inst/i_occamy/i_clint/i_sync_edge/i_sync/reg_q_reg[0]/D]
+set_false_path -to [get_pins hemaia_system_i/occamy_chip/inst/i_occamy/i_clint/i_sync_edge/i_sync/reg_q_reg[0]/D]
 
 ################################################################################
 # JTAG

target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl_ext_jtag.xdc

@@ -7,7 +7,7 @@
 # This constraint file is written for VCU128 + FMC XM105 Debug Card and is included only when EXT_JTAG = 1
 
 # 5 MHz max JTAG
-create_clock -period 200 -name jtag_tck_i [get_pins occamy_vcu128_i/jtag_tck_i]
+create_clock -period 200 -name jtag_tck_i [get_pins hemaia_system_i/jtag_tck_i]
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_pins jtag_tck_i_IBUF_inst/O]]
 set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_pins jtag_tck_i_IBUF_inst/O]]
 set_input_jitter jtag_tck_i 1.000

target/rtl/Makefile

@@ -283,7 +283,7 @@ $(TARGET_CLINT_DIR)/clint.%: $(SOURCE_CLINT_DIR)/data/clint.%.tpl $(CFG) | $(TAR
 ###########################################
 # TODO: This SNAX_CFGS should not be fixed! It should be created dynamically instead. 
 SNAX_CFGS += cfg/cluster_cfg/snax_KUL_cluster.hjson
-SNAX_CFGS += cfg/cluster_cfg/snax_streamer_gemmX_xdma_cluster.hjson
+SNAX_CFGS += cfg/cluster_cfg/snax_KUL_xdma_cluster.hjson
 
 #######################
 # Step 1: Wrapper Gen #
@@ -302,20 +302,16 @@ SNAX_CFGS += cfg/cluster_cfg/snax_streamer_gemmX_xdma_cluster.hjson
 #############################
 
 SNAX_ACC_GEN:
-ifeq ($(findstring snax_streamer_gemm_add_c_cluster,$(SNAX_CFGS)),snax_streamer_gemm_add_c_cluster)
-	$(eval BENDER_TARGETS += -t snax_streamer_gemm_add_c -t snax_streamer_gemm_add_c_cluster)
-endif
-
-ifeq ($(findstring snax_streamer_gemmX_xdma_cluster,$(SNAX_CFGS)),snax_streamer_gemmX_xdma_cluster)
-	$(eval BENDER_TARGETS += -t snax_streamer_gemmX_xdma -t snax_streamer_gemmX_xdma_cluster)
-endif
-
 ifeq ($(findstring snax_xdma_cluster,$(SNAX_CFGS)),snax_xdma_cluster)
 	$(eval BENDER_TARGETS += -t snax_xdma -t snax_xdma_cluster)
 endif
 
 ifeq ($(findstring snax_KUL_cluster,$(SNAX_CFGS)),snax_KUL_cluster)
-	$(eval BENDER_TARGETS += -t snax_KUL_cluster)
+	$(eval BENDER_TARGETS += -t snax_gemmX -t snax_data_reshuffler -t snax_KUL_cluster)
+endif
+
+ifeq ($(findstring snax_KUL_xdma_cluster,$(SNAX_CFGS)),snax_KUL_xdma_cluster)
+	$(eval BENDER_TARGETS += -t snax_gemmX -t snax_KUL_xdma_cluster_xdma -t snax_KUL_xdma_cluster)
 endif
 
 # Create the dependency in SNAX: when generating snax, the bender target should be stored into file, which will be used by other targets (e.g. tapeout, fpga, simulation)

target/rtl/cfg/cluster_cfg/snax_KUL_cluster.hjson

@@ -12,21 +12,28 @@
     cluster: {
         name: "snax_KUL_cluster",
         boot_addr: 4096, // 0x1000
-        cluster_base_addr: 268435456, // 0x1000_0000
-        cluster_base_offset: 262144,  // 256KB
+        cluster_base_addr: 268435456,  // 0x1000_0000
+        cluster_base_offset: 1048576,  // 256KB -> 1MB
         cluster_base_hartid: 1,
         addr_width: 48,
         data_width: 64,
         user_width: 5,
         tcdm: {
-            size: 128,
+            size: 512,                  // 128K -> 512K
             banks: 32,
         },
         cluster_periph_size: 64, // kB
         zero_mem_size: 64, // kB
         dma_data_width: 512,
         dma_axi_req_fifo_depth: 16,
         dma_req_fifo_depth: 8,
+        snax_custom_tcdm_assign: {
+            snax_enable_assign_tcdm_idx: true,
+            snax_narrow_assign_start_idx: [0,56],
+            snax_narrow_assign_end_idx: [7,71],
+            snax_wide_assign_start_idx: [8],
+            snax_wide_assign_end_idx: [55],
+        },
         // AXI bandwidth switcher
         use_ax_bw_converter: false,
         converted_axi_bandwidth: 256,
@@ -111,9 +118,8 @@
         xfvec: false,
         snax_acc_cfg: {
             snax_acc_name: "snax_streamer_gemmX",
-            // add a checker here?
-            // some of the tcdm ports specificed here?
-            snax_narrow_tcdm_ports: 56,
+            snax_narrow_tcdm_ports: 8,
+            snax_wide_tcdm_ports: 48,
             snax_num_rw_csr: 10,
             snax_num_ro_csr: 2,
             snax_streamer_cfg: {$ref: "#/snax_streamer_gemmX_streamer_template" }
@@ -125,9 +131,7 @@
         num_fp_outstanding_mem: 4,
         num_sequencer_instructions: 16,
         num_dtlb_entries: 1,
-        num_itlb_entries: 1,
-        // Enable division/square root unit
-        // Xdiv_sqrt: true,
+        num_itlb_entries: 1
     },
     // Templates.
     snax_data_reshuffler_core_template: {
@@ -155,14 +159,10 @@
         num_fp_outstanding_mem: 4,
         num_sequencer_instructions: 16,
         num_dtlb_entries: 1,
-        num_itlb_entries: 1,
-        // Enable division/square root unit
-        // Xdiv_sqrt: true,
+        num_itlb_entries: 1
     },
     dma_core_template: {
         isa: "rv32ima",
-        // Xdiv_sqrt: true,
-        # isa: "rv32ema",
         xdma: true
         xssr: false
         xfrep: false
@@ -178,7 +178,7 @@
         num_fp_outstanding_mem: 4,
         num_sequencer_instructions: 16,
         num_dtlb_entries: 1,
-        num_itlb_entries: 1,
+        num_itlb_entries: 1
     },
     // SNAX Streamer Templates
     snax_streamer_gemmX_streamer_template :{