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Bug Fix
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IveanEx committed Oct 8, 2024
1 parent 76ac8a7 commit c491185
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Showing 3 changed files with 19 additions and 4 deletions.
2 changes: 1 addition & 1 deletion hw/occamy/occamy_chip.sv.tpl
Original file line number Diff line number Diff line change
Expand Up @@ -49,8 +49,8 @@ import ${name}_pkg::*;
output logic [1:0] spim_csb_o,
output logic [1:0] spim_csb_en_o,
output logic [3:0] spim_sd_o,
output logic [3:0] spim_sd_en_o,
input [3:0] spim_sd_i,
output logic [3:0] spim_sd_en_o,
<%
spi_slave_present = any(periph["name"] == "spi_slave" for periph in occamy_cfg["peripherals"]["axi_lite_peripherals"])
%>
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19 changes: 17 additions & 2 deletions hw/occamy/occamy_xilinx.sv.tpl
Original file line number Diff line number Diff line change
Expand Up @@ -41,8 +41,23 @@ import ${name}_pkg::*;
inout logic i2c_scl_io,
// `SPI Host` Interface
output logic spim_sck_o,
output logic spim_sck_en_o,
output logic [1:0] spim_csb_o,
inout logic [3:0] spim_sd_io,
output logic [1:0] spim_csb_en_o,
output logic [3:0] spim_sd_o,
input [3:0] spim_sd_i,
output logic [3:0] spim_sd_en_o,
<%
spi_slave_present = any(periph["name"] == "spi_slave" for periph in occamy_cfg["peripherals"]["axi_lite_peripherals"])
%>
% if spi_slave_present:
// `SPI Slave` for Debugging Purposes
input logic spis_sck_i,
input logic spis_csb_i,
output logic [3:0] spis_sd_o,
output logic [3:0] spis_sd_en_o,
input logic [3:0] spis_sd_i,
% endif

input logic [11:0] ext_irq_i,

Expand All @@ -53,7 +68,7 @@ import ${name}_pkg::*;
output logic [47:0] bootrom_addr_o,
input logic [31:0] bootrom_data_i,

// SPM / SRAM as the main memory
// HBM Port
${soc_wide_xbar.out_spm_wide.emit_flat_master_port("m_axi_ram")}
);

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2 changes: 1 addition & 1 deletion target/rtl/test/testharness.sv.tpl
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ module testharness import occamy_pkg::*; (

// verilog_lint: waive explicit-parameter-storage-type
localparam RTCTCK = 30.518us; // 32.768 kHz
localparam SPITCK = 15.15ns; // SPI clock
localparam SPITCK = 16ns; // SPI clock

logic rtc_i;

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