Initial Push - Seperate Chiplet Generation

hw/occamy/occamy_chip.sv.tpl

@@ -19,6 +19,15 @@ import ${name}_pkg::*;
   input  logic        test_mode_i,
   input  chip_id_t    chip_id_i,
   input  logic [1:0]  boot_mode_i,
+% if occamy_cfg['hemaia_multichip']['single_chip'] is False: 
+  // HeMAiA D2D AXI Interface
+  // Chiplet Requst to Router
+  output ${soc2router_bus.req_type()} soc2router_req_o,
+  input  ${soc2router_bus.rsp_type()} soc2router_rsp_i,
+  // Router Requst to Chiplet
+  input  ${router2soc_bus.req_type()} router2soc_req_i,
+  output ${router2soc_bus.rsp_type()} router2soc_rsp_o,
+% endif
   // `uart` Interface
   output logic        uart_tx_o,
   input  logic        uart_rx_i,
@@ -160,6 +169,14 @@ import ${name}_pkg::*;
     .rtc_i              (rtc_i),
     .test_mode_i        (test_mode_i),
     .chip_id_i          (chip_id_i),
+% if occamy_cfg['hemaia_multichip']['single_chip'] is False: 
+    // Chiplet Requst to Router
+    .soc2router_req_o,
+    .soc2router_rsp_i,
+    // Router Requst to Chiplet
+    .router2soc_req_i,
+    .router2soc_rsp_o,
+% endif
     .boot_mode_i        (boot_mode_i),
     .uart_tx_o          (uart_tx_o),
     .uart_cts_ni        (uart_cts_ni),

hw/occamy/occamy_soc.sv.tpl

@@ -8,6 +8,8 @@
 // AUTOMATICALLY GENERATED by genoccamy.py; edit the script instead.
 
 <%
+  cuts_soc_to_router = occamy_cfg["cuts"]["soc_to_router"]
+  cuts_router_to_soc = occamy_cfg["cuts"]["router_to_soc"]
   cuts_narrow_to_quad = occamy_cfg["cuts"]["narrow_to_quad"]
   cuts_quad_to_narrow = occamy_cfg["cuts"]["quad_to_narrow"]
   cuts_wide_to_quad = occamy_cfg["cuts"]["wide_to_quad"]
@@ -59,6 +61,16 @@ module ${name}_soc
   output ${soc_wide_xbar.out_spm_wide.req_type()} spm_axi_wide_req_o,
   input  ${soc_wide_xbar.out_spm_wide.rsp_type()} spm_axi_wide_rsp_i,
 
+% if occamy_cfg['hemaia_multichip']['single_chip'] is False: 
+  // HeMAiA Multi-Chip AXI Interface
+  // Chiplet Requst to Router
+  output ${soc2router_bus.req_type()} soc2router_req_o,
+  input  ${soc2router_bus.rsp_type()} soc2router_rsp_i,
+  // Router Requst to Chiplet
+  input  ${router2soc_bus.req_type()} router2soc_req_i,
+  output ${router2soc_bus.rsp_type()} router2soc_rsp_o,
+% endif
+
   // SoC control register IO
   output logic [1:0] spm_narrow_rerror_o,
   output logic [1:0] spm_wide_rerror_o,
@@ -80,6 +92,24 @@ module ${name}_soc
 
   ${module}
 
+% if occamy_cfg['hemaia_multichip']['single_chip'] is False: 
+  ///////////////////////////////////////
+  // Connections between SoC to Router //
+  ///////////////////////////////////////
+  <% 
+    soc2router = soc_wide_xbar.out_hemaia_multichip \
+                  .change_iw(context, soc2router_bus.iw, "soc2router_iwc") \
+                  .cut(context, cuts_soc_to_router, name="soc2router_cut")
+    router2soc = soc_wide_xbar.in_hemaia_multichip \
+                  .change_iw(context, router2soc_bus.iw, "router2soc_iwc") \
+                  .cut(context, cuts_router_to_soc, name="router2soc_cut")
+  %> \
+  assign soc2router_req_o = ${soc2router.req_name()};
+  assign ${soc2router.rsp_name()} = soc2router_rsp_i;
+  assign ${router2soc.req_name()} = router2soc_req_i;
+  assign router2soc_rsp_o = ${router2soc.rsp_name()};
+% endif
+
   ///////////////////////////////////
   // Connections between crossbars //
   ///////////////////////////////////
@@ -233,7 +263,7 @@ module ${name}_soc
   // SPM WIDE //
   //////////////
   <% wide_spm_mst = soc_wide_xbar.out_spm_wide \
-                    .cut(context, cuts_wide_conv_to_spm_wide)
+                    .cut(context, cuts_wide_conv_to_spm_wide, name="wide_spm_cut")
   %>\
 
   assign spm_axi_wide_req_o = ${wide_spm_mst.req_name()};

hw/occamy/occamy_top.sv.tpl

@@ -72,6 +72,16 @@ module ${name}_top
   output ${soc_wide_xbar.out_spm_wide.req_type()} spm_axi_wide_req_o,
   input  ${soc_wide_xbar.out_spm_wide.rsp_type()} spm_axi_wide_rsp_i,
 
+% if occamy_cfg['hemaia_multichip']['single_chip'] is False: 
+  // HeMAiA Multi-Chip AXI Interface
+  // Chiplet Requst to Router
+  output ${soc2router_bus.req_type()} soc2router_req_o,
+  input  ${soc2router_bus.rsp_type()} soc2router_rsp_i,
+  // Router Requst to Chiplet
+  input  ${router2soc_bus.req_type()} router2soc_req_i,
+  output ${router2soc_bus.rsp_type()} router2soc_rsp_o,
+% endif
+
   /// Chip specific control registers
   output ${soc_axi_lite_narrow_periph_xbar.out_chip_ctrl.req_type()} chip_ctrl_req_o,
   input  ${soc_axi_lite_narrow_periph_xbar.out_chip_ctrl.rsp_type()} chip_ctrl_rsp_i,
@@ -83,7 +93,6 @@ module ${name}_top
 );
 
 <%
-
   cuts_clint_cfg = occamy_cfg["cuts"]["periph_axi_lite_narrow_clint_cfg"]
   cuts_soc_ctrl_cfg = occamy_cfg["cuts"]["periph_axi_lite_narrow_soc_ctrl_cfg"]
   cuts_chip_ctrl_cfg = occamy_cfg["cuts"]["periph_axi_lite_narrow_chip_ctrl_cfg"]
@@ -153,6 +162,14 @@ module ${name}_top
     .periph_axi_lite_narrow_rsp_i ( periph_regbus_soc2per_rsp ),
     .spm_axi_wide_req_o,
     .spm_axi_wide_rsp_i,
+% if occamy_cfg['hemaia_multichip']['single_chip'] is False: 
+    // Chiplet Requst to Router
+    .soc2router_req_o,
+    .soc2router_rsp_i,
+    // Router Requst to Chiplet
+    .router2soc_req_i,
+    .router2soc_rsp_o,
+% endif
     .spm_narrow_rerror_o (spm_narrow_rerror),
     .spm_wide_rerror_o (spm_wide_rerror),
     .mtip_i ( mtip ),

target/rtl/cfg/hemaia.hjson

@@ -6,7 +6,9 @@
     // Multi-chip configuration
     hemaia_multichip: {
       chip_id_width: 8, 
-      single_chip: false,
+      router_to_soc_iw: 8,
+      soc_to_router_iw: 4,
+      single_chip: true,
       single_chip_id: 0, 
       testbench_cfg: {
         // Emulate a four-chips configuration
@@ -34,6 +36,8 @@
       fall_through: false,
     },
     cuts: {
+      soc_to_router: 1,
+      router_to_soc: 1,
       narrow_to_quad: 3,
       quad_to_narrow: 3,
       wide_to_quad: 3,
@@ -116,7 +120,6 @@
     },
     clusters:[
       "snax_KUL_cluster",
-      "snax_KUL_xdma_cluster",
       "snax_hypercorex_cluster",
       // "snax_dimc_cluster"
     ],

target/rtl/cfg/hemaia_tapeout.hjson → target/rtl/cfg/hemaia_chiplet.hjson

@@ -6,7 +6,9 @@
     // Multi-chip configuration
     hemaia_multichip: {
       chip_id_width: 8, 
-      single_chip: true,
+      router_to_soc_iw: 8,
+      soc_to_router_iw: 4,
+      single_chip: false,
       single_chip_id: 0, 
       testbench_cfg: {
         // Emulate a four-chips configuration
@@ -34,6 +36,8 @@
       fall_through: false,
     },
     cuts: {
+      soc_to_router: 1,
+      router_to_soc: 1,
       narrow_to_quad: 3,
       quad_to_narrow: 3,
       wide_to_quad: 3,
@@ -115,10 +119,9 @@
       cfg_base_offset: 65536 // 0x10000
     },
     clusters:[
-      "snax_cgra_cluster",
-      "snax_KUL_xdma_cluster",
+      "snax_KUL_cluster",
       "snax_hypercorex_cluster",
-      "snax_dimc_cluster"
+      // "snax_dimc_cluster"
     ],
 
     // peripherals