Fix Addess Rule in chip_antwerp (#99)

* Fix Addess Rule in chip_antwerp * Update occamygen * Bug Fix
KULeuven-MICAS · Dec 10, 2024 · ac1cbfb · ac1cbfb
1 parent 27cd30b
commit ac1cbfb
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Showing 2 changed files with 7 additions and 9 deletions.
diff --git a/util/occamygen/occamygen.py b/util/occamygen/occamygen.py
@@ -335,7 +335,7 @@ def main():
         # Default route passes HBI through quadrant 0
         # --> mask this route, forcing it through default wide xbar
         soc_wide_xbar.add_output_entry("quadrant_{}".format(i),
-                                       am_wide_xbar_quadrant_s1[i])
+                                am_wide_xbar_quadrant_s1[i])
         soc_wide_xbar.add_input("quadrant_{}".format(i))
 
     ###################
@@ -357,13 +357,11 @@ def main():
         node=am_soc_narrow_xbar)
 
     for i in range(nr_s1_quadrants):
-        # soc_narrow_xbar.add_output_symbolic_multi("s1_quadrant_{}".format(i),
-        #                                           [("s1_quadrant_base_addr",
-        #                                             "S1QuadrantAddressSpace"),
-        #                                            ("s1_quadrant_cfg_base_addr",
-        #                                             "S1QuadrantCfgAddressSpace")])
-        soc_narrow_xbar.add_output_entry(
-            "s1_quadrant_{}".format(i), am_narrow_xbar_quadrant_s1[i])
+        soc_narrow_xbar.add_output_symbolic_multi("s1_quadrant_{}".format(i),
+                                                  [("ClusterBaseOffset",
+                                                    "S1QuadrantAddressSpace"),
+                                                   ("S1QuadrantCfgBaseOffset",
+                                                    "S1QuadrantCfgAddressSpace")])
         soc_narrow_xbar.add_input("s1_quadrant_{}".format(i))
 
     soc_narrow_xbar.add_input("cva6")

diff --git a/util/solder/solder.py b/util/solder/solder.py
@@ -1591,7 +1591,7 @@ def emit(self):
         for i, (idx, entries) in enumerate(self.symbolic_addrmap_multi):
             for base, length in entries:
                 addrmap_lines.append(
-                    "  '{{ idx: {}, start_addr: {}[{i}], end_addr: {}[{i}] + {} }}".format(
+                    "  '{{ idx: {}, start_addr: {}, end_addr: {} + {} }}".format(
                         idx, base, base, length, i=i))
         addrmap += "{}\n}};\n".format(',\n'.join(addrmap_lines))