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Sync PR#62-#65 (#77)
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* Update Bender.yml (#62)

* Update occamy_chip.sv.tpl (#63)

* Update SPI Testbench to support multiple read / write demands (#64)

* fix chip connection (#65)

* Fix Chip Connection

* Update HeMAiA FPGA Config

---------

Co-authored-by: Fanchen Kong <[email protected]>
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@IveanEx @Konste11ation
IveanEx and Konste11ation authored Nov 2, 2024
1 parent 9c9dea6 commit 3b17fdb
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Showing 9 changed files with 137 additions and 242 deletions.
1 change: 1 addition & 0 deletions Bender.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -130,4 +130,5 @@ sources:

- target: tsmc_pad
files:
- /users/micas/shares/project_snax/tapeout_modules/hemaia/obs_clk_div.sv
- /users/micas/shares/project_snax/tapeout_modules/hemaia/hemaia_chip_top.sv
22 changes: 11 additions & 11 deletions hw/occamy/occamy_chip.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -151,15 +151,15 @@ import ${name}_pkg::*;
///////////////////

${name}_top i_${name} (
.clk_i, (clk_i),
.rst_ni, (rst_ni),
.clk_i (clk_i),
.rst_ni (rst_ni),
.sram_cfgs_i ('0),
.clk_periph_i, (clk_periph_i),
.rst_periph_ni, (rst_periph_ni),
.rtc_i, (rtc_i),
.test_mode_i (1'b0),
.chip_id_i (chip_id),
.boot_mode_i ('0),
.clk_periph_i (clk_periph_i),
.rst_periph_ni (rst_periph_ni),
.rtc_i (rtc_i),
.test_mode_i (test_mode_i),
.chip_id_i (chip_id_i),
.boot_mode_i (boot_mode_i),
.uart_tx_o (uart_tx_o),
.uart_cts_ni (uart_cts_ni),
.uart_rts_no (uart_rts_no),
Expand All @@ -173,18 +173,18 @@ import ${name}_pkg::*;
.jtag_tdi_i (jtag_tdi_i),
.jtag_tdo_o (jtag_tdo_o),
.i2c_sda_o (),
.i2c_scl_i ('0),
.i2c_sda_i ('1),
.i2c_sda_en_o (),
.i2c_scl_o (),
.i2c_scl_i ('0),
.i2c_scl_i ('1),
.i2c_scl_en_o (),
.spim_sck_o (),
.spim_sck_en_o (),
.spim_csb_o (),
.spim_csb_en_o (),
.spim_sd_o (),
.spim_sd_en_o (),
.spim_sd_i ('0),
.spim_sd_i ('1),
% if spi_slave_present:
.spis_sck_i (spis_sck_i),
.spis_csb_i (spis_csb_i),
Expand Down
66 changes: 32 additions & 34 deletions target/fpga/occamy_vcu128_impl.xdc
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Original file line number Diff line number Diff line change
Expand Up @@ -16,38 +16,38 @@ set_property IOSTANDARD LVCMOS18 [get_ports uart_cts_ni]
set_property PACKAGE_PIN BP23 [get_ports uart_rts_no]
set_property IOSTANDARD LVCMOS18 [get_ports uart_rts_no]

# Six-wires SPIx4
# LA10_P - B23
set_property PACKAGE_PIN B23 [get_ports spim_sd_io[0]]
set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[0]]
# LA10_N - A23
set_property PACKAGE_PIN A23 [get_ports spim_sd_io[1]]
set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[1]]
# LA11_P - B26
set_property PACKAGE_PIN B26 [get_ports spim_sd_io[2]]
set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[2]]
# LA11_N - B25
set_property PACKAGE_PIN B25 [get_ports spim_sd_io[3]]
set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[3]]
# LA12_P - J22
set_property PACKAGE_PIN J22 [get_ports spim_csb_o[0]]
set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[0]]
# LA12_N - H22
set_property PACKAGE_PIN H22 [get_ports spim_csb_o[1]]
set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[1]]
# LA13_P - A25
set_property PACKAGE_PIN A25 [get_ports spim_sck_o]
set_property IOSTANDARD LVCMOS18 [get_ports spim_sck_o]

create_clock -period 20.000 -name spi_m_sck [get_ports spim_sck_o]

# Two-wires I2C
# LA14_P - C23
set_property PACKAGE_PIN C23 [get_ports i2c_sda_io]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda_io]
# LA14_N - B22
set_property PACKAGE_PIN B22 [get_ports i2c_scl_io]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl_io]
# # Six-wires SPIx4
# # LA10_P - B23
# set_property PACKAGE_PIN B23 [get_ports spim_sd_io[0]]
# set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[0]]
# # LA10_N - A23
# set_property PACKAGE_PIN A23 [get_ports spim_sd_io[1]]
# set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[1]]
# # LA11_P - B26
# set_property PACKAGE_PIN B26 [get_ports spim_sd_io[2]]
# set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[2]]
# # LA11_N - B25
# set_property PACKAGE_PIN B25 [get_ports spim_sd_io[3]]
# set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[3]]
# # LA12_P - J22
# set_property PACKAGE_PIN J22 [get_ports spim_csb_o[0]]
# set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[0]]
# # LA12_N - H22
# set_property PACKAGE_PIN H22 [get_ports spim_csb_o[1]]
# set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[1]]
# # LA13_P - A25
# set_property PACKAGE_PIN A25 [get_ports spim_sck_o]
# set_property IOSTANDARD LVCMOS18 [get_ports spim_sck_o]

# create_clock -period 20.000 -name spi_m_sck [get_ports spim_sck_o]

# # Two-wires I2C
# # LA14_P - C23
# set_property PACKAGE_PIN C23 [get_ports i2c_sda_io]
# set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda_io]
# # LA14_N - B22
# set_property PACKAGE_PIN B22 [get_ports i2c_scl_io]
# set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl_io]

# Six-wires SPIx4 (Slave)
# LA15_N - H20
Expand Down Expand Up @@ -145,5 +145,3 @@ set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 127.5 [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]


45 changes: 1 addition & 44 deletions target/fpga_chip/hemaia_system/hemaia_system_vcu128_bd.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -223,12 +223,7 @@ proc create_root_design { parentCell } {
set jtag_tck_i [ create_bd_port -dir I -type clk -freq_hz 5000000 jtag_tck_i ]
set uart_cts_ni [ create_bd_port -dir I uart_cts_ni ]
set uart_rts_no [ create_bd_port -dir O uart_rts_no ]
set spim_sck_o [ create_bd_port -dir O spim_sck_o ]
set gpio_d_o [ create_bd_port -dir O -from 7 -to 0 gpio_d_o ]
set spim_csb_o [ create_bd_port -dir O -from 1 -to 0 spim_csb_o ]
set i2c_sda_io [ create_bd_port -dir IO i2c_sda_io ]
set i2c_scl_io [ create_bd_port -dir IO i2c_scl_io ]
set spim_sd_io [ create_bd_port -dir IO -from 3 -to 0 spim_sd_io ]
set spis_sck_i [ create_bd_port -dir I spis_sck_i ]
set spis_csb_i [ create_bd_port -dir I spis_csb_i ]
set spis_sd_io [ create_bd_port -dir IO -from 3 -to 0 spis_sd_io ]
Expand Down Expand Up @@ -326,14 +321,6 @@ proc create_root_design { parentCell } {
# Create instance: occamy_chip, and set properties
set occamy_chip [ create_bd_cell -type ip -vlnv MICAS_KUL:user:occamy_chip:1.0 occamy_chip ]

# Create instance: spim_iobuf, and set properties
set spim_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 spim_iobuf ]
set_property -dict [list \
CONFIG.C_BUF_TYPE {IOBUF} \
CONFIG.C_SIZE {4} \
] $spim_iobuf


# Create instance: spis_iobuf, and set properties
set spis_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 spis_iobuf ]
set_property -dict [list \
Expand All @@ -342,37 +329,16 @@ proc create_root_design { parentCell } {
] $spis_iobuf


# Create instance: i2c_sda_iobuf, and set properties
set i2c_sda_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 i2c_sda_iobuf ]
set_property -dict [list \
CONFIG.C_BUF_TYPE {IOBUF} \
CONFIG.C_SIZE {1} \
] $i2c_sda_iobuf


# Create instance: i2c_scl_iobuf, and set properties
set i2c_scl_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 i2c_scl_iobuf ]
set_property -dict [list \
CONFIG.C_BUF_TYPE {IOBUF} \
CONFIG.C_SIZE {1} \
] $i2c_scl_iobuf


# Create interface connections
connect_bd_intf_net -intf_net default_100mhz_clk_1 [get_bd_intf_ports default_100mhz_clk] [get_bd_intf_pins clk_wiz/CLK_IN1_D]

# Create port connections
connect_bd_net -net Net [get_bd_ports spis_sd_io] [get_bd_pins spis_iobuf/IOBUF_IO_IO]
connect_bd_net -net Net1 [get_bd_ports i2c_sda_io] [get_bd_pins i2c_sda_iobuf/IOBUF_IO_IO]
connect_bd_net -net Net2 [get_bd_ports i2c_scl_io] [get_bd_pins i2c_scl_iobuf/IOBUF_IO_IO]
connect_bd_net -net Net3 [get_bd_ports spim_sd_io] [get_bd_pins spim_iobuf/IOBUF_IO_IO]
connect_bd_net -net bootmode [get_bd_pins vio_sys/probe_out1] [get_bd_pins occamy_chip/boot_mode_i]
connect_bd_net -net c_high_dout [get_bd_pins c_high/dout] [get_bd_ports vref_vdd_o] [get_bd_pins occamy_chip/jtag_trst_ni]
connect_bd_net -net clk_wiz_clk_core [get_bd_pins clk_wiz/clk_core] [get_bd_pins vio_sys/clk] [get_bd_pins occamy_chip/clk_i] [get_bd_pins occamy_chip/clk_periph_i]
connect_bd_net -net clk_wiz_clk_rtc [get_bd_pins clk_wiz/clk_rtc] [get_bd_pins occamy_chip/rtc_i]
connect_bd_net -net const_low_dout [get_bd_pins c_low/dout] [get_bd_ports vref_gnd_o] [get_bd_pins occamy_chip/test_mode_i] [get_bd_pins occamy_chip/ext_irq_i] [get_bd_pins occamy_chip/gpio_d_i]
connect_bd_net -net i2c_scl_iobuf_IOBUF_IO_O [get_bd_pins i2c_sda_iobuf/IOBUF_IO_O] [get_bd_pins occamy_chip/i2c_sda_i]
connect_bd_net -net i2c_scl_iobuf_IOBUF_IO_O1 [get_bd_pins i2c_scl_iobuf/IOBUF_IO_O] [get_bd_pins occamy_chip/i2c_scl_i]
connect_bd_net -net const_low_dout [get_bd_pins c_low/dout] [get_bd_ports vref_gnd_o] [get_bd_pins occamy_chip/test_mode_i] [get_bd_pins occamy_chip/gpio_d_i]
connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins occamy_chip/jtag_tck_i]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets jtag_tck_i_1]
connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins occamy_chip/jtag_tdi_i]
Expand All @@ -382,25 +348,16 @@ proc create_root_design { parentCell } {
connect_bd_net -net occamy_chip_0_gpio_d_o [get_bd_pins occamy_chip/gpio_d_o] [get_bd_pins xlslice_1/Din]
connect_bd_net -net occamy_chip_0_jtag_tdo_o [get_bd_pins occamy_chip/jtag_tdo_o] [get_bd_ports jtag_tdo_o]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_jtag_tdo_o]
connect_bd_net -net occamy_chip_0_spim_csb_o [get_bd_pins occamy_chip/spim_csb_o] [get_bd_ports spim_csb_o]
connect_bd_net -net occamy_chip_0_spim_sck_o [get_bd_pins occamy_chip/spim_sck_o] [get_bd_ports spim_sck_o]
connect_bd_net -net occamy_chip_0_uart_rts_no [get_bd_pins occamy_chip/uart_rts_no] [get_bd_ports uart_rts_no]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_uart_rts_no]
connect_bd_net -net occamy_chip_0_uart_tx_o [get_bd_pins occamy_chip/uart_tx_o] [get_bd_ports uart_tx_o]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_uart_tx_o]
connect_bd_net -net occamy_chip_i2c_scl_en_o [get_bd_pins occamy_chip/i2c_scl_en_o] [get_bd_pins i2c_scl_iobuf/IOBUF_IO_T]
connect_bd_net -net occamy_chip_i2c_scl_o [get_bd_pins occamy_chip/i2c_scl_o] [get_bd_pins i2c_scl_iobuf/IOBUF_IO_I]
connect_bd_net -net occamy_chip_i2c_sda_en_o [get_bd_pins occamy_chip/i2c_sda_en_o] [get_bd_pins i2c_sda_iobuf/IOBUF_IO_T]
connect_bd_net -net occamy_chip_i2c_sda_o [get_bd_pins occamy_chip/i2c_sda_o] [get_bd_pins i2c_sda_iobuf/IOBUF_IO_I]
connect_bd_net -net occamy_chip_spim_sd_en_o [get_bd_pins occamy_chip/spim_sd_en_o] [get_bd_pins spim_iobuf/IOBUF_IO_T]
connect_bd_net -net occamy_chip_spim_sd_o [get_bd_pins occamy_chip/spim_sd_o] [get_bd_pins spim_iobuf/IOBUF_IO_I]
connect_bd_net -net occamy_chip_spis_sd_en_o [get_bd_pins occamy_chip/spis_sd_en_o] [get_bd_pins spis_iobuf/IOBUF_IO_T]
connect_bd_net -net occamy_chip_spis_sd_o [get_bd_pins occamy_chip/spis_sd_o] [get_bd_pins spis_iobuf/IOBUF_IO_I]
connect_bd_net -net occamy_rst [get_bd_pins rst_or_core/Res] [get_bd_pins rst_core_inv/Op1]
connect_bd_net -net occamy_rstn [get_bd_pins rst_core_inv/Res] [get_bd_pins occamy_chip/rst_ni] [get_bd_pins occamy_chip/rst_periph_ni]
connect_bd_net -net reset [get_bd_pins vio_sys/probe_out0] [get_bd_pins concat_rst_core/In1]
connect_bd_net -net reset_button [get_bd_ports reset] [get_bd_pins concat_rst_core/In0]
connect_bd_net -net spim_iobuf_IOBUF_IO_O [get_bd_pins spim_iobuf/IOBUF_IO_O] [get_bd_pins occamy_chip/spim_sd_i]
connect_bd_net -net spis_csb_i_0_1 [get_bd_ports spis_csb_i] [get_bd_pins occamy_chip/spis_csb_i]
connect_bd_net -net spis_iobuf_IOBUF_IO_O [get_bd_pins spis_iobuf/IOBUF_IO_O] [get_bd_pins occamy_chip/spis_sd_i]
connect_bd_net -net spis_sck_i_0_1 [get_bd_ports spis_sck_i] [get_bd_pins occamy_chip/spis_sck_i]
Expand Down
33 changes: 0 additions & 33 deletions target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl.xdc
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Original file line number Diff line number Diff line change
Expand Up @@ -33,39 +33,6 @@ set_property PULLUP TRUE [get_ports uart_cts_ni]
set_property PACKAGE_PIN D21 [get_ports uart_rts_no]
set_property IOSTANDARD LVCMOS18 [get_ports uart_rts_no]

# Six-wires SPIx4 (Master)
# LA10_P - B23
set_property PACKAGE_PIN B23 [get_ports spim_sd_io[0]]
set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[0]]
# LA10_N - A23
set_property PACKAGE_PIN A23 [get_ports spim_sd_io[1]]
set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[1]]
# LA11_P - B26
set_property PACKAGE_PIN B26 [get_ports spim_sd_io[2]]
set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[2]]
# LA11_N - B25
set_property PACKAGE_PIN B25 [get_ports spim_sd_io[3]]
set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[3]]
# LA12_P - J22
set_property PACKAGE_PIN J22 [get_ports spim_csb_o[0]]
set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[0]]
# LA12_N - H22
set_property PACKAGE_PIN H22 [get_ports spim_csb_o[1]]
set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[1]]
# LA13_P - A25
set_property PACKAGE_PIN A25 [get_ports spim_sck_o]
set_property IOSTANDARD LVCMOS18 [get_ports spim_sck_o]

create_clock -period 20.000 -name spi_m_sck [get_ports spim_sck_o]

# Two-wires I2C
# LA14_P - C23
set_property PACKAGE_PIN C23 [get_ports i2c_sda_io]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda_io]
# LA14_N - B22
set_property PACKAGE_PIN B22 [get_ports i2c_scl_io]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl_io]

# Six-wires SPIx4 (Slave)
# LA15_N - H20
set_property PACKAGE_PIN H20 [get_ports spis_sd_io[0]]
Expand Down
35 changes: 0 additions & 35 deletions target/fpga_chip/hemaia_system/hemaia_system_vpk180_bd.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -218,12 +218,7 @@ proc create_root_design { parentCell } {
set jtag_tck_i [ create_bd_port -dir I -type clk -freq_hz 5000000 jtag_tck_i ]
set uart_cts_ni [ create_bd_port -dir I uart_cts_ni ]
set uart_rts_no [ create_bd_port -dir O uart_rts_no ]
set spim_sck_o [ create_bd_port -dir O spim_sck_o ]
set gpio_d_o [ create_bd_port -dir O -from 3 -to 0 gpio_d_o ]
set spim_csb_o [ create_bd_port -dir O -from 1 -to 0 spim_csb_o ]
set i2c_sda_io [ create_bd_port -dir IO i2c_sda_io ]
set i2c_scl_io [ create_bd_port -dir IO i2c_scl_io ]
set spim_sd_io [ create_bd_port -dir IO -from 3 -to 0 spim_sd_io ]
set spis_sd_io [ create_bd_port -dir IO -from 3 -to 0 spis_sd_io ]
set spis_sck_i [ create_bd_port -dir I spis_sck_i ]
set spis_csb_i [ create_bd_port -dir I spis_csb_i ]
Expand Down Expand Up @@ -338,24 +333,6 @@ proc create_root_design { parentCell } {
] $versal_cips_0


# Create instance: i2c_scl_iobuf, and set properties
set i2c_scl_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 i2c_scl_iobuf ]
set_property CONFIG.C_BUF_TYPE {IOBUF} $i2c_scl_iobuf


# Create instance: i2c_sda_iobuf, and set properties
set i2c_sda_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 i2c_sda_iobuf ]
set_property CONFIG.C_BUF_TYPE {IOBUF} $i2c_sda_iobuf


# Create instance: spim_iobuf, and set properties
set spim_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 spim_iobuf ]
set_property -dict [list \
CONFIG.C_BUF_TYPE {IOBUF} \
CONFIG.C_SIZE {4} \
] $spim_iobuf


# Create instance: spis_iobuf, and set properties
set spis_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 spis_iobuf ]
set_property -dict [list \
Expand All @@ -365,9 +342,6 @@ proc create_root_design { parentCell } {


# Create port connections
connect_bd_net -net Net [get_bd_ports spim_sd_io] [get_bd_pins spim_iobuf/IOBUF_IO_IO]
connect_bd_net -net Net1 [get_bd_ports i2c_scl_io] [get_bd_pins i2c_scl_iobuf/IOBUF_IO_IO]
connect_bd_net -net Net2 [get_bd_ports i2c_sda_io] [get_bd_pins i2c_sda_iobuf/IOBUF_IO_IO]
connect_bd_net -net Net3 [get_bd_ports spis_sd_io] [get_bd_pins spis_iobuf/IOBUF_IO_IO]
connect_bd_net -net bootmode [get_bd_pins axis_vio_0/probe_out1] [get_bd_pins occamy_chip/boot_mode_i]
connect_bd_net -net c_high_dout [get_bd_pins c_high/dout] [get_bd_ports vref_vdd_o] [get_bd_pins occamy_chip/jtag_trst_ni]
Expand All @@ -384,25 +358,16 @@ proc create_root_design { parentCell } {
connect_bd_net -net occamy_chip_0_gpio_d_o [get_bd_pins occamy_chip/gpio_d_o] [get_bd_pins xlslice_1/Din]
connect_bd_net -net occamy_chip_0_jtag_tdo_o [get_bd_pins occamy_chip/jtag_tdo_o] [get_bd_ports jtag_tdo_o]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_jtag_tdo_o]
connect_bd_net -net occamy_chip_0_spim_csb_o [get_bd_pins occamy_chip/spim_csb_o] [get_bd_ports spim_csb_o]
connect_bd_net -net occamy_chip_0_spim_sck_o [get_bd_pins occamy_chip/spim_sck_o] [get_bd_ports spim_sck_o]
connect_bd_net -net occamy_chip_0_uart_rts_no [get_bd_pins occamy_chip/uart_rts_no] [get_bd_ports uart_rts_no]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_uart_rts_no]
connect_bd_net -net occamy_chip_0_uart_tx_o [get_bd_pins occamy_chip/uart_tx_o] [get_bd_ports uart_tx_o]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_uart_tx_o]
connect_bd_net -net occamy_chip_i2c_scl_en_o [get_bd_pins occamy_chip/i2c_scl_en_o] [get_bd_pins i2c_scl_iobuf/IOBUF_IO_T]
connect_bd_net -net occamy_chip_i2c_scl_o [get_bd_pins occamy_chip/i2c_scl_o] [get_bd_pins i2c_scl_iobuf/IOBUF_IO_I]
connect_bd_net -net occamy_chip_i2c_sda_en_o [get_bd_pins occamy_chip/i2c_sda_en_o] [get_bd_pins i2c_sda_iobuf/IOBUF_IO_T]
connect_bd_net -net occamy_chip_i2c_sda_o [get_bd_pins occamy_chip/i2c_sda_o] [get_bd_pins i2c_sda_iobuf/IOBUF_IO_I]
connect_bd_net -net occamy_chip_spim_sd_en_o [get_bd_pins occamy_chip/spim_sd_en_o] [get_bd_pins spim_iobuf/IOBUF_IO_T]
connect_bd_net -net occamy_chip_spim_sd_o [get_bd_pins occamy_chip/spim_sd_o] [get_bd_pins spim_iobuf/IOBUF_IO_I]
connect_bd_net -net occamy_chip_spis_sd_en_o [get_bd_pins occamy_chip/spis_sd_en_o] [get_bd_pins spis_iobuf/IOBUF_IO_T]
connect_bd_net -net occamy_chip_spis_sd_o [get_bd_pins occamy_chip/spis_sd_o] [get_bd_pins spis_iobuf/IOBUF_IO_I]
connect_bd_net -net occamy_rst [get_bd_pins rst_or_core/Res] [get_bd_pins rst_core_inv/Op1]
connect_bd_net -net occamy_rstn [get_bd_pins rst_core_inv/Res] [get_bd_pins occamy_chip/rst_ni] [get_bd_pins occamy_chip/rst_periph_ni]
connect_bd_net -net reset [get_bd_pins axis_vio_0/probe_out0] [get_bd_pins concat_rst_core/In1]
connect_bd_net -net reset_button [get_bd_ports reset] [get_bd_pins concat_rst_core/In0]
connect_bd_net -net spim_iobuf_IOBUF_IO_O [get_bd_pins spim_iobuf/IOBUF_IO_O] [get_bd_pins occamy_chip/spim_sd_i]
connect_bd_net -net spis_csb_i_0_1 [get_bd_ports spis_csb_i] [get_bd_pins occamy_chip/spis_csb_i]
connect_bd_net -net spis_iobuf_IOBUF_IO_O [get_bd_pins spis_iobuf/IOBUF_IO_O] [get_bd_pins occamy_chip/spis_sd_i]
connect_bd_net -net spis_sck_i_0_1 [get_bd_ports spis_sck_i] [get_bd_pins occamy_chip/spis_sck_i]
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