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@Konste11ation
Konste11ation committed Oct 8, 2024
1 parent f0165cd commit 12a41d8
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Showing 7 changed files with 8 additions and 138 deletions.
24 changes: 1 addition & 23 deletions hw/spm_interface/src/spm_1p_adv.sv
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Expand Up @@ -181,28 +181,6 @@ module spm_1p_adv #(
.rdata_o(rdata_sram)
);

// tc_sram_impl #(
// .NumWords (NumWords),
// .DataWidth(SPMDataWidth),
// .ByteWidth(ByteWidth),
// .NumPorts (1),
// .SimInit (SimInit),
// .PrintSimCfg (PrintSimCfg),
// .Latency (1),
// .impl_in_t (sram_cfg_t)
// ) i_mem (
// .clk_i(clk_i),
// .rst_ni(rst_ni),
// .impl_i (sram_cfg_i),
// .impl_o ( ),
// .req_i(req_q),
// .we_i(we_q),
// .addr_i(addr_q),
// .wdata_i(wdata_q),
// .be_i(be_q),
// .rdata_o(rdata_sram)
// );

always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rvalid_sram_q <= 1'b0;
Expand Down Expand Up @@ -272,4 +250,4 @@ module spm_1p_adv #(
assign rerror_q = rerror_d & {2{rvalid_d}};
end

endmodule
endmodule
2 changes: 1 addition & 1 deletion hw/spm_interface/src/spm_1p_adv_mem_wrapper.sv
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Expand Up @@ -63,4 +63,4 @@ module spm_1p_adv_mem_wrapper #(
.rdata_o(rdata_o)
);

endmodule
endmodule
54 changes: 2 additions & 52 deletions hw/vendor/openhwgroup_cva6/core/cache_subsystem/cva6_icache.sv
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Expand Up @@ -476,57 +476,6 @@ end else begin : gen_piton_offset
assign cl_ruser[i] = '0;
end



// for (genvar i = 0; i < ICACHE_SET_ASSOC; i++) begin : gen_sram
// // Tag RAM
// tc_sram_impl #(
// .impl_in_t ( sram_cfg_t ),
// // tag + valid bit
// .DataWidth ( ICACHE_TAG_WIDTH+1 ),
// .NumWords ( ICACHE_NUM_WORDS ),
// .NumPorts ( 1 )
// ) tag_sram (
// .clk_i ( clk_i ),
// .rst_ni ( rst_ni ),
// .impl_i ( sram_cfg_tag_i ),
// .impl_o ( ),
// .req_i ( vld_req[i] ),
// .we_i ( vld_we ),
// .addr_i ( vld_addr ),
// // we can always use the saved tag here since it takes a
// // couple of cycle until we write to the cache upon a miss
// .wdata_i ( {vld_wdata[i], cl_tag_q} ),
// .be_i ( '1 ),
// .rdata_o ( cl_tag_valid_rdata[i] )
// );

// assign cl_tag_rdata[i] = cl_tag_valid_rdata[i][ICACHE_TAG_WIDTH-1:0];
// assign vld_rdata[i] = cl_tag_valid_rdata[i][ICACHE_TAG_WIDTH];

// // Data RAM
// tc_sram_impl #(
// .impl_in_t ( sram_cfg_t ),
// .DataWidth ( ICACHE_LINE_WIDTH ),
// .NumWords ( ICACHE_NUM_WORDS ),
// .NumPorts ( 1 )
// ) data_sram (
// .clk_i ( clk_i ),
// .rst_ni ( rst_ni ),
// .impl_i ( sram_cfg_data_i ),
// .impl_o ( ),
// .req_i ( cl_req[i] ),
// .we_i ( cl_we ),
// .addr_i ( cl_index ),
// .wdata_i ( mem_rtrn_i.data ),
// .be_i ( '1 ),
// .rdata_o ( cl_rdata[i] )
// );

// assign cl_ruser[i] = '0;
// end


always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
if(!rst_ni) begin
cl_tag_q <= '0;
Expand Down Expand Up @@ -611,4 +560,5 @@ end else begin : gen_piton_offset
`endif
//pragma translate_on

endmodule // cva6_icache
endmodule
// cva6_icache
60 changes: 1 addition & 59 deletions hw/vendor/openhwgroup_cva6/core/cache_subsystem/std_nbdcache.sv
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Expand Up @@ -232,45 +232,6 @@ import std_cache_pkg::*;
assign rdata_ram[i].data = rdata_ram_data[i];
assign rdata_ram[i].tag = rdata_ram_tag[i];
end
// for (genvar i = 0; i < DCACHE_SET_ASSOC; i++) begin : sram_block
// tc_sram_impl #(
// .impl_in_t ( sram_cfg_t ),
// .DataWidth ( DCACHE_LINE_WIDTH ),
// .NumWords ( DCACHE_NUM_WORDS ),
// .NumPorts ( 1 )
// ) data_sram (
// .req_i ( req_ram [i] ),
// .rst_ni ( rst_ni ),
// .impl_i ( sram_cfg_data_i ),
// .impl_o ( ),
// .we_i ( we_ram ),
// .addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ),
// .wdata_i ( wdata_ram.data ),
// .be_i ( be_ram.data ),
// .rdata_o ( rdata_ram[i].data ),
// .*
// );

// tc_sram_impl #(
// .impl_in_t ( sram_cfg_t ),
// .DataWidth ( DCACHE_TAG_WIDTH ),
// .NumWords ( DCACHE_NUM_WORDS ),
// .NumPorts ( 1 )
// ) tag_sram (
// .req_i ( req_ram [i] ),
// .rst_ni ( rst_ni ),
// .impl_i ( sram_cfg_tag_i ),
// .impl_o ( ),
// .we_i ( we_ram ),
// .addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ),
// .wdata_i ( wdata_ram.tag ),
// .be_i ( be_ram.tag ),
// .rdata_o ( rdata_ram[i].tag ),
// .*
// );

// end

// ----------------
// Valid/Dirty Regs
// ----------------
Expand Down Expand Up @@ -304,25 +265,6 @@ import std_cache_pkg::*;
.rdata_o ( dirty_rdata )
);


// tc_sram_impl #(
// .impl_in_t ( sram_cfg_t ),
// .DataWidth ( 4*DCACHE_DIRTY_WIDTH ),
// .NumWords ( DCACHE_NUM_WORDS ),
// .NumPorts ( 1 )
// ) valid_dirty_sram (
// .clk_i ( clk_i ),
// .rst_ni ( rst_ni ),
// .impl_i ( sram_cfg_valid_dirty_i ),
// .impl_o ( ),
// .req_i ( |req_ram ),
// .we_i ( we_ram ),
// .addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ),
// .wdata_i ( dirty_wdata ),
// .be_i ( be_ram.vldrty ),
// .rdata_o ( dirty_rdata )
// );

// ------------------------------------------------
// Tag Comparison and memory arbitration
// ------------------------------------------------
Expand Down Expand Up @@ -356,4 +298,4 @@ import std_cache_pkg::*;
assert (DCACHE_LINE_WIDTH/AXI_DATA_WIDTH inside {2, 4, 8, 16}) else $fatal(1, "Cache line size needs to be a power of two multiple of AXI_DATA_WIDTH");
end
//pragma translate_on
endmodule
endmodule
2 changes: 1 addition & 1 deletion hw/vendor/openhwgroup_cva6/core/cache_subsystem/std_nbdcache_data.sv
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Expand Up @@ -66,4 +66,4 @@ module std_nbdcache_data #(
);
end

endmodule
endmodule
2 changes: 1 addition & 1 deletion hw/vendor/openhwgroup_cva6/core/cache_subsystem/std_nbdcache_tag.sv
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Expand Up @@ -66,4 +66,4 @@ module std_nbdcache_tag #(
);
end

endmodule
endmodule
2 changes: 1 addition & 1 deletion hw/vendor/openhwgroup_cva6/core/cache_subsystem/std_nbdcache_valid_dirty.sv
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Expand Up @@ -64,4 +64,4 @@ module std_nbdcache_valid_dirty #(
.rdata_o ( rdata_o )
);

endmodule
endmodule

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