Welcome to my 100 Days of RTL Challenge repository! 🎉
In this project, I will be coding various digital designs using Verilog and RTL design techniques as part of a 100-day challenge to improve my hardware description language (HDL) skills.
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Day 1: Basic Gates using Behavioral Design
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Day 2: Basic Gates using Structural Design
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Day 3: Basic Gates using Gate Level Design
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Day 4: MOS Inverter Design & Testbench
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Day 5: Random Boolean Expression (ABC + A'C' + D)
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Day 6: Half Adder & Full Adder
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Day 7: Half Subtractor & Full Subtractor
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Day 8: 4-bit Parallel Adder with Control Input
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Day 9: 16-BIT ADDER AND SUBTRACTOR with Control input.
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Day 10: Ripple Carry Adder using 4 Full Adders
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Day 11: 4-bit Binary Multiplier with Adder-Based Partial Product Summation
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Day 12: Half Adder, Full Adder, Half Subtractor, Full Subtractor using Nand Gate
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Day 13: BCD adder Using Verilog.
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Day 14: 4 Bit Divider
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Day 15: 4 Bit Magnitude Comparator
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Day 16: Carry Look Ahead Generator
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Day 17: Carry Select Adder
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Day 18: Carry Save Adder
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Day 19: Carry Skip Adder
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Day 20: Even Parity Generator and Checker
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Day 21: N bit Comparator
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Day 22: Multiplexer [2:1]
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Day 23: [4:1] Mux using [2:1]
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Day 24: 16x1 Mux using 2x1 Mux by instantiating in Verilog.
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Day 25: K:1 Mux using parameter statement (K=64)
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Day 26: Logic Gates using Mux
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Day 27: Full Adder using Mux
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Day 28: DeMultiplexer [1:2]
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Day 29: DeMultiplexer[1:8] using [1:2]
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Day 30: 1:32 Demultiplexer Using Verilog.
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Day 31: Logic Gates using Dmux
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Day 32: 1-Bit Comparator Using 4x1 Mux.
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Day 33: Octal to binary Converter - Encoder [8:3]
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Day 34: Priority Encoder
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Day 35: Decoder [3:8]
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Day 36: 3x8 Decoder using 2x4 Decoder.
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Day 37: 5x32 Decoder using Verilog.
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Day 38: BCD to Decimal Decoder
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Day 39: watchdog timer (WDT)
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Day 40: Monostable Multivibrator
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Day 41: Input Majority Circuit [7 input]
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Day 42: Binary to Gray code Converter
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Day 43: Gray code to Binary Converter
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Day 44: Binary to BCD Converter
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Day 45: BCD to 7-Segment Converter
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Day 46: SR Latch
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Day 47: JK Flip Flop
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Day 48: D Flip Flop
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Day 49: T Flip Flop
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Day 50: Arithmetic Logic Unit (ALU)
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Day 51: SR flip flop using JK, D, T flip flops
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Day 52: JK flip flop using SR, D, T flip flops
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Day 53: D flip flop using SR, JK, T flip flops
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Day 54: T flip flop using SR, JK, D flip flops
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Day 55: Serial in Serial out (SISO) Register
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Day 56: Serial in Parallel out (SIPO) Register
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Day 57: Parallel in Serial out (PISO) Register
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Day 58: Parallel in Parallel out (PIPO) Register
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Day 59: Serial-in Serial-Out Shift Register Using JK Flip-Flop.
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Day 60: Linear Feedback Shift Register (LFSR)
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Day 61: Universal Shift Register
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Day 62: Barrel Shifter
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Day 63: Booth's Multiplication Algorithm
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Day 64: Vedic Multiplier [4×4] using [2×2]
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Day 65: Mod-N Counter
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Day 66: Specific Sequence Counter
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Day 67: Up/Down Counter
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Day 68: Ring Counter
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Day 69: Johnson Couter
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Day 70: Clock Edge Detector
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Day 71: Frequency Divider {even}
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Day 72: Frequency Divider {odd}
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Day 73: Frequency Divider {decimal}
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Day 74: Two sequence detector using FSM
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Day 75: 16x16 Register File
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Day 76: Cache Memory (Direct Mapping)
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Day 77: Checking if Number is an Even or Odd Number
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Day 78: *Checking if Number is a Prime Number *
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Day 79: Checking if Number is a Pallindrome Number
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Day 80: Checking if Number is an Armstrong Number
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... (Tasks will be added as I progress)
- Vivado 2024.1 🛠️
- The designs will be synthesized and simulated using the latest version of Xilinx Vivado (2024.1).
This project is licensed under the MIT License. See the LICENSE file for details.