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axi_agent: Adapt the verbosity for each display
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Signed-off-by: Alae Eddine Ez zejjari <[email protected]>
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@AEzzejjari
AEzzejjari committed Mar 3, 2023
1 parent fdab858 commit bbedad1
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Showing 12 changed files with 24 additions and 25 deletions.
1 change: 1 addition & 0 deletions lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv
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Expand Up @@ -104,6 +104,7 @@ class uvma_axi_agent_c extends uvm_agent;

if (cfg.trn_log_enabled) begin
connect_trn_loggers();
`uvm_info(get_type_name(), $sformatf("Transaction Loger enable"), UVM_LOW)
end

endfunction
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2 changes: 1 addition & 1 deletion lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_drv.sv
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Expand Up @@ -76,7 +76,7 @@ class uvma_axi_ar_drv_c extends uvm_driver #(uvma_axi_ar_item_c);
end
this.slave_mp.slv_axi_cb.ar_ready <= 1'b1;
end
`uvm_info(get_type_name(), $sformatf("read address, response by ar_ready"), UVM_LOW)
`uvm_info(get_type_name(), $sformatf("read address, response by ar_ready"), UVM_HIGH)
@(slave_mp.slv_axi_cb);
this.slave_mp.slv_axi_cb.ar_ready <= 1'b0;
seq_item_port.item_done();
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2 changes: 1 addition & 1 deletion lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_drv.sv
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Expand Up @@ -81,7 +81,7 @@ endtask: drv_in_reset

task uvma_axi_aw_drv_c::drv_post_reset();

`uvm_info(get_type_name(), $sformatf("write address driver start"), UVM_LOW)
`uvm_info(get_type_name(), $sformatf("write address driver start"), UVM_HIGH)
seq_item_port.get_next_item(aw_item);

this.slave_mp.slv_axi_cb.aw_ready <= 1'b0;
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2 changes: 1 addition & 1 deletion lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_drv.sv
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Expand Up @@ -82,7 +82,7 @@ class uvma_axi_b_drv_c extends uvm_driver #(uvma_axi_b_item_c);

seq_item_port.get_next_item(b_item);

`uvm_info(get_type_name(),$sformatf("response, send resp to DUT"), UVM_LOW)
`uvm_info(get_type_name(),$sformatf("response, send resp to DUT"), UVM_HIGH)

this.slave_mp.slv_axi_cb.b_id <= this.b_item.b_id;
this.slave_mp.slv_axi_cb.b_resp <= this.b_item.b_resp;
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2 changes: 1 addition & 1 deletion lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv
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Expand Up @@ -78,7 +78,7 @@ task uvma_axi_b_mon_c::monitor_b_items();
forever begin

// collect b signals
`uvm_info(get_type_name(), $sformatf("response, collect resp signals from interface"), UVM_LOW)
`uvm_info(get_type_name(), $sformatf("response, collect resp signals from interface"), UVM_HIGH)
this.b_item.b_id = passive_mp.psv_axi_cb.b_id;
this.b_item.b_resp = passive_mp.psv_axi_cb.b_resp;
this.b_item.b_user = passive_mp.psv_axi_cb.b_user;
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2 changes: 1 addition & 1 deletion lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_drv.sv
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Expand Up @@ -90,7 +90,7 @@ task uvma_axi_r_drv_c::drv_post_reset();

seq_item_port.get_next_item(r_item);

`uvm_info(get_type_name(),$sformatf("response, send data to DUT"), UVM_LOW)
`uvm_info(get_type_name(),$sformatf("response, send data to DUT"), UVM_HIGH)
this.slave_mp.slv_axi_cb.r_id <= this.r_item.r_id;
this.slave_mp.slv_axi_cb.r_resp <= this.r_item.r_resp;
this.slave_mp.slv_axi_cb.r_user <= this.r_item.r_user;
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2 changes: 1 addition & 1 deletion lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_drv.sv
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Expand Up @@ -93,7 +93,7 @@ endtask: drv_in_reset
task uvma_axi_w_drv_c::drv_post_reset();

seq_item_port.get_next_item(w_item);
`uvm_info(get_type_name(), $sformatf("write data driver start"), UVM_LOW)
`uvm_info(get_type_name(), $sformatf("write data driver start"), UVM_HIGH)
this.slave_mp.slv_axi_cb.w_ready <= w_item.w_ready;
@(slave_mp.slv_axi_cb);
seq_item_port.item_done();
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4 changes: 2 additions & 2 deletions lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_seq.sv
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Expand Up @@ -50,11 +50,11 @@ task uvma_axi_ar_seq_c::body();
p_sequencer.ar_req_fifo.get(req_item);

start_item(req_item);
`uvm_info(get_type_name(), "READ ADDRESS sequence starting", UVM_LOW)
`uvm_info(get_type_name(), "READ ADDRESS sequence starting", UVM_HIGH)
add_latencies(req_item);
finish_item(req_item);
end
`uvm_info(get_type_name(), "Default sequence completed", UVM_LOW)
`uvm_info(get_type_name(), "Default sequence completed", UVM_HIGH)

endtask : body

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4 changes: 2 additions & 2 deletions lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_seq.sv
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Expand Up @@ -51,12 +51,12 @@ task uvma_axi_aw_seq_c::body();
p_sequencer.aw_req_fifo.get(req_item);

start_item(req_item);
`uvm_info(get_type_name(), "WRITE ADDRESS sequence starting", UVM_LOW)
`uvm_info(get_type_name(), "WRITE ADDRESS sequence starting", UVM_HIGH)
add_latencies(req_item);
finish_item(req_item);

end
`uvm_info(get_type_name(), "Default sequence completed", UVM_LOW)
`uvm_info(get_type_name(), "Default sequence completed", UVM_HIGH)

endtask : body

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4 changes: 2 additions & 2 deletions lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_seq.sv
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Expand Up @@ -67,7 +67,7 @@ task uvma_axi_b_seq_c::body();
cfg = p_sequencer.cfg ;
cntxt = p_sequencer.cntxt;

`uvm_info(get_type_name(), "WRITE RESPONSE sequence starting", UVM_LOW)
`uvm_info(get_type_name(), "WRITE RESPONSE sequence starting", UVM_HIGH)

p_sequencer.aw_req_export.get(aw_req_item);
p_sequencer.w_req_export.get(w_req_item);
Expand Down Expand Up @@ -174,7 +174,7 @@ task uvma_axi_b_seq_c::body();
end

finish_item(b_resp_item);
`uvm_info(get_type_name(), "Default sequence completed", UVM_LOW)
`uvm_info(get_type_name(), "Default sequence completed", UVM_HIGH)
end
endtask : body

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15 changes: 7 additions & 8 deletions lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_seq.sv
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Expand Up @@ -72,7 +72,7 @@ task uvma_axi_r_seq_c::body();
cfg = p_sequencer.cfg ;
cntxt = p_sequencer.cntxt;

`uvm_info(get_type_name(), "READ DATA sequence starting", UVM_LOW)
`uvm_info(get_type_name(), "READ DATA sequence starting", UVM_HIGH)

p_sequencer.ar_req_export.get(req_item);
p_sequencer.r_resp_fifo.get(pre_resp);
Expand All @@ -81,7 +81,7 @@ task uvma_axi_r_seq_c::body();

if(req_item.ar_valid && req_item.ar_ready) begin

`uvm_info(get_type_name(), "Read request registere", UVM_LOW)
`uvm_info(get_type_name(), "Read request registere", UVM_HIGH)
if(req_item.ar_id >= ar_id_tr.size()) begin

ar_id_tr = new[req_item.ar_id+1] (ar_id_tr);
Expand All @@ -97,7 +97,7 @@ task uvma_axi_r_seq_c::body();
req_requette[req_item.ar_id][ar_id_tr[req_item.ar_id] - 1] = new req_item;

end
`uvm_info(get_type_name(), "Read request registred", UVM_LOW)
`uvm_info(get_type_name(), "Read request registred", UVM_HIGH)
status = new[status.size() + 1] (status);
status[status.size() - 1] = req_item.ar_id;
end
Expand All @@ -108,10 +108,9 @@ task uvma_axi_r_seq_c::body();
r_latency = -1;
end

`uvm_info(get_type_name(), $sformatf("r_ready id = %d || LATENCY = %d",pre_resp.r_ready, r_latency), UVM_LOW)
if(r_latency > -1 && pre_resp.r_ready && selected_id != -1) begin

`uvm_info(get_type_name(), "transfert termine", UVM_LOW)
`uvm_info(get_type_name(), "transfert termine", UVM_HIGH)
if(ar_id_tr[selected_id] > 0) begin
if(resp_item.r_last == 1'b1) begin

Expand Down Expand Up @@ -143,12 +142,12 @@ task uvma_axi_r_seq_c::body();

end

`uvm_info(get_type_name(), $sformatf("selected id = %d || LATENCY = %d",selected_id, r_latency), UVM_LOW)
`uvm_info(get_type_name(), $sformatf("selected id = %d || LATENCY = %d",selected_id, r_latency), UVM_HIGH)

if(selected_id != -1) begin
if(r_latency == -1) begin

`uvm_info(get_type_name(), "read item", UVM_LOW)
`uvm_info(get_type_name(), "read item", UVM_HIGH)
prepare_resp(req_requette[selected_id][0], resp_item, inject_error);
if(req_requette[selected_id][0].ar_len == 0) begin
`uvm_info(get_type_name()," last will be asserted ",UVM_HIGH)
Expand All @@ -173,7 +172,7 @@ task uvma_axi_r_seq_c::body();

finish_item(resp_item);
end
`uvm_info(get_type_name(), "Default sequence completed", UVM_LOW)
`uvm_info(get_type_name(), "Default sequence completed", UVM_HIGH)

endtask : body

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9 changes: 4 additions & 5 deletions lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_seq.sv
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Expand Up @@ -63,7 +63,7 @@ task uvma_axi_w_seq_c::body();
cfg = p_sequencer.cfg;
cntxt = p_sequencer.cntxt;

`uvm_info(get_type_name(), "WRITE DATA sequence starting", UVM_LOW)
`uvm_info(get_type_name(), "WRITE DATA sequence starting", UVM_HIGH)

p_sequencer.aw_req_export.get(aw_req_item);
p_sequencer.w_req_fifo.get(w_req_item);
Expand Down Expand Up @@ -95,7 +95,6 @@ task uvma_axi_w_seq_c::body();
end

start_item(w_req_item);
`uvm_info(get_type_name(), $sformatf("req_requette size = %d", req_requette.size()), UVM_LOW)
if(w_req_item.w_valid) begin

if(latency == 0) begin
Expand All @@ -122,11 +121,11 @@ task uvma_axi_w_seq_c::body();
w_req_item.w_ready = 0;
end

`uvm_info(get_type_name(), $sformatf("status = %d et write_status = %d", status, write_status), UVM_LOW)
`uvm_info(get_type_name(), $sformatf("status = %d et write_status = %d", status, write_status), UVM_HIGH)
if(status == 1 && write_status == 1) begin

longint aligned_addr;
`uvm_info(get_type_name(), $sformatf("AXI_ADDR_WIDTH = %d et AXI_ADDR_WIDTH_BYTE = %d", AXI_ADDR_WIDTH, AXI_ADDR_WIDTH/8), UVM_LOW)
`uvm_info(get_type_name(), $sformatf("AXI_ADDR_WIDTH = %d et AXI_ADDR_WIDTH_BYTE = %d", AXI_ADDR_WIDTH, AXI_ADDR_WIDTH/8), UVM_HIGH)
aligned_addr = req_requette[0].aw_addr - req_requette[0].aw_addr % (AXI_ADDR_WIDTH/8);
if(write_data_req[0].w_strb[0]) cntxt.mem.write(aligned_addr+0, write_data_req[0].w_data[07:00]);
if(write_data_req[0].w_strb[1]) cntxt.mem.write(aligned_addr+1, write_data_req[0].w_data[15:08]);
Expand Down Expand Up @@ -162,7 +161,7 @@ task uvma_axi_w_seq_c::body();
end
finish_item(w_req_item);
end
`uvm_info(get_type_name(), "Write data sequence completed", UVM_LOW)
`uvm_info(get_type_name(), "Write data sequence completed", UVM_HIGH)

endtask : body

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