Merge pull request openhwgroup#1745 from AyoubJalali/core_dev

CVA6 DV : Add a configuration bit (enable_x_extension) to generate the right .include

cva6/env/corev-dv/cva6_asm_program_gen.sv

@@ -38,7 +38,11 @@ class cva6_asm_program_gen_c extends riscv_asm_program_gen;
 
    virtual function void gen_program_header();
       string str[$];
-      instr_stream.push_back(".include \"user_define.include\"");
+      cva6_instr_gen_config_c cfg_cva6;
+      `DV_CHECK_FATAL($cast(cfg_cva6, cfg), "Could not cast cfg into cfg_cva6")
+      if (cfg_cva6.enable_x_extension) begin //used for cvxif custom test
+         instr_stream.push_back(".include \"x_extn_user_define.h\"");
+      end
       instr_stream.push_back(".include \"user_define.h\"");
       instr_stream.push_back(".globl _start");
       instr_stream.push_back(".section .text");

cva6/env/corev-dv/cva6_instr_base_test.sv

@@ -0,0 +1,54 @@
+/*
+ * Copyright 2018 Google LLC
+ * Copyright 2020 OpenHW Group
+ * Copyright 2023 Thales
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//------------------------------------------------------------------------------
+// CORE-V instruction generator base test:
+//     - extension of the RISC-V instruction generator base test.
+//
+//------------------------------------------------------------------------------
+
+class cva6_instr_base_test_c extends riscv_instr_base_test;
+
+  `uvm_component_utils(cva6_instr_base_test_c)
+
+
+  function new(string name="", uvm_component parent=null);
+    super.new(name, parent);
+  endfunction
+
+  virtual function void build_phase(uvm_phase phase);
+    override_asm_program_gen();
+    override_gen_config();
+    super.build_phase(phase);
+  endfunction
+
+  virtual function void override_asm_program_gen();
+    `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW)
+    uvm_factory::get().set_type_override_by_type(riscv_asm_program_gen::get_type(),
+                                                 cva6_asm_program_gen_c::get_type());
+    `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW)
+  endfunction
+
+  virtual function void override_gen_config();
+    `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW)
+    uvm_factory::get().set_type_override_by_type(riscv_instr_gen_config::get_type(),
+                                                 cva6_instr_gen_config_c::get_type());
+    `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW)
+  endfunction
+
+endclass : cva6_instr_base_test_c

cva6/env/corev-dv/cva6_instr_gen_config.sv

@@ -0,0 +1,40 @@
+/*
+ * Copyright 2018 Google LLC
+ * Copyright 2023 Thales
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//-----------------------------------------------------------------------------
+// RISC-V assembly program generator configuration class
+//-----------------------------------------------------------------------------
+
+class cva6_instr_gen_config_c extends riscv_instr_gen_config;
+
+  //-----------------------------------------------------------------------------
+  // Random instruction generation option
+  //-----------------------------------------------------------------------------
+
+  // cvxif extension support
+  bit                     enable_x_extension ;
+
+    `uvm_object_utils_begin(cva6_instr_gen_config_c)
+      `uvm_field_int(enable_x_extension, UVM_DEFAULT)
+    `uvm_object_utils_end
+
+  function new (string name = "");
+    super.new(name);
+    get_bool_arg_value("+enable_x_extension=", enable_x_extension);
+  endfunction
+
+endclass : cva6_instr_gen_config_c

cva6/env/corev-dv/cva6_instr_test_pkg.sv

@@ -16,4 +16,8 @@ package cva6_instr_test_pkg;
    import riscv_instr_test_pkg::*;
    import cva6_instr_pkg::*;
 
+   `include "cva6_instr_gen_config.sv"
+   `include "cva6_asm_program_gen.sv"
+   `include "cva6_instr_base_test.sv"
+
 endpackage : cva6_instr_test_pkg;