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Merged main:b83b28779ee56236aaf8827398f889334abbd28d into amd-gfx:667…
…0c73ea871 Local branch amd-gfx 6670c73 [AMDGPU][Waterfall] Put exec save in the loop header Remote branch main b83b287 [RISCV] Make Zhinx and Zvfh imply Zhinxmin and Zvfhmin respectively (llvm#75735)
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Original file line number | Diff line number | Diff line change |
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//===- IntrinsicsRISCVXCV.td - CORE-V intrinsics -----------*- tablegen -*-===// | ||
// | ||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
// See https://llvm.org/LICENSE.txt for license information. | ||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
// | ||
//===----------------------------------------------------------------------===// | ||
// | ||
// This file defines all of the CORE-V vendor intrinsics for RISC-V. | ||
// | ||
//===----------------------------------------------------------------------===// | ||
|
||
class ScalarCoreVBitManipGprGprIntrinsic | ||
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], | ||
[IntrNoMem, IntrSpeculatable]>; | ||
|
||
class ScalarCoreVBitManipGprIntrinsic | ||
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], | ||
[IntrNoMem, IntrSpeculatable]>; | ||
|
||
let TargetPrefix = "riscv" in { | ||
def int_riscv_cv_bitmanip_extract : ScalarCoreVBitManipGprGprIntrinsic; | ||
def int_riscv_cv_bitmanip_extractu : ScalarCoreVBitManipGprGprIntrinsic; | ||
def int_riscv_cv_bitmanip_bclr : ScalarCoreVBitManipGprGprIntrinsic; | ||
def int_riscv_cv_bitmanip_bset : ScalarCoreVBitManipGprGprIntrinsic; | ||
|
||
def int_riscv_cv_bitmanip_insert | ||
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], | ||
[IntrNoMem, IntrSpeculatable]>; | ||
|
||
def int_riscv_cv_bitmanip_clb : ScalarCoreVBitManipGprIntrinsic; | ||
|
||
def int_riscv_cv_bitmanip_bitrev | ||
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], | ||
[IntrNoMem, IntrWillReturn, IntrSpeculatable, | ||
ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; | ||
} // TargetPrefix = "riscv" |
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