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Icestudio nightly build version
Juan Gonzalez-Gomez edited this page Nov 19, 2020
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Every Nightly build version comes with a version notes, where the more important features are hightlighted
- Location: icestudio/app/views/version.html
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Images: icestudio/app/resources/images/version-notes/0.5.1n201120
- The folder at the end has the name of the release version. Inside that folder all the images references from the version.html file are placed
- The file version.html should be renamed to version-tag.html, where tag is the version descriptor of the previous nightly (e.x 5.1n201120)
- Start a new version.html for the current nightly version
- Add the new tag version in the files:
- icestudio/package.json, package-lock.json
- icestudio/app/package.json, package-lock.json
- Default: Icestudio Default Collection
- IceK: Constants
- IceWires: Wires and Buses
- IceIO: FPGA IO-pins
- IceGates: Logic gates
- IceMux: Muxes and demuxes
- IceCoders: Binary Encoders and Decoders
- IceFF: Flip-Flops
- IceRegs: Registers
- IceSRegs: Shift Registers
- IceBoards: blocks and examples for the diferent FPGA boards
- IceComp: Comparators
- IceArith: Integer arithmetics
- IceCounter: Counters
- IceSignals: 1-bit signal managment
- IcePLL: PLLs
- IceLEDOscope: Measuring signals
- IceLEDs: Displaying on LEDs
- IceHearts: Timming signal generation
- IceInputs: 1-bit inputs
- IceRok: Block probes for Icestudio => Sigrok integration (with Pulseview GUI)
- IceMachines: Working with Machines (simple state machines with a standar interface)
- IceSerial: Serial Asynchronous communications
- IceMem: Working with Memories
- IceMeasure: Measuring cycles and time in your circuits, very easily
- IceStack: Working with stacks
- IceFlash: Read from spi serial flash memories
- IceBus: Accesing and sharing simple buses
- IceLCD: Components and controllers for LCDs
- IceUnary: Working with unary numbers
- IceCrystal: Drive displays from Open Source FPGAs
- ice-chips-verilog: IceChips is a library of all common discrete logic devices in Verilog
- ArithmeticBlocks: FPGA signed and unsigned integer operations, 16, 24 and 32 bits, + - * / sqrt min max compare etc.
- iceSynth: Audio synthesis
- icebreaker: Blocks and examples for the icebreaker OpenFPGA board
- Jedi: blocks of the FPGA Jedi hardware Academy
- LOVE-FPGA: Hardware elements and examples for the LOVE-FPGA project (Linking Of Virtual Electronics to FPGAs)
- Stdio: Standard Input-Output in different devices
- CT11: Ejemplos del cuaderno ténico 11: Señales del sistema y Medición con el LEDOscopio
- Generic: Icestudio Generic Collection
- Logic: Icestudio Logic Collection
- IceInterface: Serial, SPI, I2C... (TODO)
- IceK-TB: Tests for iceK
- IceWires-TB: Test for icewires
- IceIO-TB: Tests for iceIO
- iceGates-TB: Tests for gates
- iceCoders-TB: Tests for iceCoders
- IceFF-TB: Tests for iceFF
- IceRegs-TB: Tests for registers
- IceSregs-TB: Tests for shift registers
- Jedi-Test: Tests for the blocks on the Jedi Collection