Merge branch 'main' of https://github.com/FPGAwars/iceWires

locale/translation.js

@@ -2060,9 +2060,17 @@ gettext('01-Manual-testing');
 gettext('## 07-Uint8: Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
-gettext('UINT12-8bit-verilog:  Extend a 8-bit unsigned integer to 12-bits. Verilog implementation ');
-gettext('UINT32-12bit-verilog:  Extend a 12-bit unsigned integer to 32-bits. Verilog implementation ');
-gettext('## Uint12-8bit Manual testing');
+gettext('Rising-edge detector. It generates a 1-period pulse (tic) when a rising edge is detected on the input. Block implementation');
+gettext('System - D Flip-flop. Capture data every system clock cycle. Verilog implementation');
+gettext('Valor genérico constante, de 1 bits. Su valor se introduce como parámetro. Por defecto vale 0');
+gettext('Edges detector. It generates a 1-period pulse (tic) when either a rising edge or a falling edge is detected on the input. Block implementation');
+gettext('DFF. D Flip-flop. Verilog implementation');
+gettext('16-Sys-reg-rst: 16 bits system register with reset. Verilog implementation');
+gettext('Sync-x01: 1-bit input with the system clock domain (Verilog implementation)');
+gettext('TFF-verilog. System TFF with toggle input: It toogles on every system cycle if the input is active. Verilog implementation');
+gettext('## 08-Uint12 Manual testing');
+gettext('# D Flip-Flop  (system)\n\nIt stores the input data that arrives at cycle n  \nIts output is shown in the cycle n+1');
+gettext('Not connected');
 gettext('08-bits');
 gettext('09-bits');
 gettext('10-bits');
@@ -2088,6 +2096,7 @@ gettext('UINT32-11bit-verilog:  Extend a 11-bit unsigned integer to 32-bits. Ver
 gettext('## Uint16-11bit Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
+gettext('UINT32-12bit-verilog:  Extend a 12-bit unsigned integer to 32-bits. Verilog implementation ');
 gettext('## Uint16-12bit Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');