Introduce debug and late debug op code support

data/languages/mcpxcode.ldefs → data/languages/xcodedbug.ldefs

@@ -7,12 +7,12 @@
    <language processor="mcpxcode"
             endian="little"
             size="32"
-            variant="default"
+            variant="DBUG"
             version="1.0"
-            slafile="mcpxcode.sla"
-            processorspec="mcpxcode.pspec"
-            id="mcpxcode:LE:32:default">
+            slafile="xcodedbug.sla"
+            processorspec="xcodedbug.pspec"
+            id="mcpxcode:LE:32:DBUG">
     <description>Skeleton Language Module</description>
-    <compiler name="default" spec="mcpxcode.cspec" id="default"/>
+    <compiler name="default" spec="xcodedbug.cspec" id="default"/>
   </language> 
 </language_definitions>

data/languages/xcodedbug.sinc

@@ -0,0 +1,140 @@
+# sleigh include file for MCPX Code language instructions
+
+define token instr (40)
+	op8 = (0,7)
+
+	cop8 = (8,15)
+
+	u32a = (8,39)
+;
+
+define token instrb (32)
+	u32b = (0, 31)
+;
+
+define pcodeop unk_op;
+define pcodeop exit;
+
+REL: reloc is u32b [ reloc = inst_next + u32b; ] {
+	export *:4 reloc;
+}
+
+CREL: reloc is epsilon [ reloc = inst_next + ACC; ] {
+	export *:4 reloc;
+}
+
+# PCI Config add to memory addr
+# 0x80000000 | bus << 16 | device << 11 | function <<  8 | offset
+#
+# mask = 0x80000880 ^ 0x80000000
+#
+# bus = (mask > 16) & 0xFF
+# device = (mask > 11) & 0x1F
+# func = (mask > 8) & 0x7
+# reg = mask & 0xFF
+#
+# target = bus << 24 | device << 16 | function << 8 | reg
+
+PCI: conf is u32a [ 
+	conf = (((u32a >> 16) & 0xFF) << 24) | (((u32a >> 11) & 0x1F) << 16) | (((u32a >> 8) & 0x7) << 8) | (u32a & 0xFF);	
+] {
+	export *[pciconf]:4 conf;
+}
+################################################################
+
+:xc_mem_read u32a is op8=0x9A & u32a ; u32b {
+	ACC = *[ram]:4 u32a:4;
+}
+
+:xc_mem_write u32a, u32b is op8=0x5B & u32a ; u32b {
+	*[ram]:4 u32a:4 = u32b:4;
+}
+
+:xc_pci_write PCI, u32b is op8=0xF9 & PCI ; u32b {
+	PCI = u32b:4;
+}
+
+:xc_pci_read PCI is op8=0xF5 & PCI ; u32b {
+	ACC = PCI;
+}
+
+:xc_andor u32a, u32b is op8=0xED & u32a ; u32b {
+	ACC = ACC & u32a:4;
+	ACC = ACC | u32b:4;
+}
+
+:xc_jne u32a, REL is op8=0x04 & u32a ; REL {
+	if ACC == u32a:4 goto REL;
+}
+
+:xc_jmp REL is op8=0x25 ; REL {
+	goto REL;
+}
+
+:xc_andorepb u32a, u32b is op8=0x6C & u32a ; u32b {
+	ACC2 = ACC2 & u32a:4;
+	ACC2 = ACC2 | u32b:4;
+}
+
+:xc_io_write u32a, u32b is op8=0x3C & u32a ; u32b {
+	*[io]:1 u32a:2 = u32b:1;
+}
+
+:xc_io_read u32a is op8=0xC8 & u32a ; u32b {
+	ACC = zext(*[io]:1 u32a:2);
+} 
+
+:xc_exit is op8=0xBF {
+	exit();
+	goto inst_start;
+}
+
+:xc_chain ^"xc_mem_read", u32b is op8=0x68 & cop8=0x9A ; u32b {
+	ACC = *:4 u32b:4;
+}
+
+:xc_chain ^"xc_mem_write", u32b is op8=0x68 & cop8=0x5B ; u32b {
+	*:4 u32b:4 = ACC:4;
+}
+
+:xc_chain ^"xc_pci_write", u32b is op8=0x68 & cop8=0xF9 ; u32b {
+	*[pciconf]:4 u32b:4 = ACC:4;
+}
+
+:xc_chain ^"xc_pci_read", u32b is op8=0x68 & cop8=0xF5 ; u32b {
+	ACC = *[pciconf]:4 u32b:4;
+}
+
+:xc_chain ^"xc_andor", u32b is op8=0x68 & cop8=0xED ; u32b {
+	ACC = ACC & u32b:4;
+	ACC = ACC | ACC;
+}
+
+:xc_chain ^"xc_jne", u32b, CREL is op8=0x68 & cop8=0x04 ; u32b & CREL {
+	if ACC == u32b:4 goto CREL;
+}
+
+:xc_chain ^"xc_jmp", CREL is op8=0x68 & cop8=0x25 ; u32b & CREL {
+	goto CREL;
+}
+
+:xc_chain ^"xc_andorepb", u32b is op8=0x68 & cop8=0x6C ; u32b {
+	ACC2 = ACC2 & u32b:4;
+	ACC2 = ACC2 | ACC;
+}
+
+:xc_chain ^"xc_io_write", u32b is op8=0x68 & cop8=0x3C ; u32b {
+	*[io]:1 u32b:2 = ACC:1;
+}
+
+:xc_chain ^"xc_io_read", u32b is op8=0x68 & cop8=0xC8 ; u32b {
+	ACC = zext(*[io]:1 u32b:2);
+}
+
+:xc_chain ^"xc_unk_"^cop8, u32b is op8=0x68 & cop8; u32b {
+	unk_op(cop8:1, u32b:4, ACC:4);
+}
+
+:xc_unk_^op8 u32a, u32b is op8 & u32a ; u32b {
+	unk_op(op8:1, u32a:4, u32b:4);
+}

data/languages/mcpxcode.slaspec → data/languages/xcodedbug.slaspec

@@ -14,4 +14,4 @@ define space register type=register_space size=1;
 
 define register offset=0x00 size=4 [ PC ACC ACC2 SP ];
 
-@include "mcpxcode.sinc"
+@include "xcodedbug.sinc"

data/languages/xcodelatedbug.cspec

@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/compiler_spec.rxg -->
+
+<compiler_spec>
+  <data_organization>
+    <absolute_max_alignment value="0" />
+    <machine_alignment value="1" />
+    <default_alignment value="1" />
+    <default_pointer_alignment value="4" />
+    <pointer_size value="4" />
+    <wchar_size value="2" />
+    <short_size value="2" />
+    <integer_size value="4" />
+    <float_size value="4" />
+    <size_alignment_map>
+      <entry size="1" alignment="1"/>
+      <entry size="2" alignment="2"/>
+      <entry size="4" alignment="4"/>
+    </size_alignment_map>
+  </data_organization>
+  <global>
+    <range space="ram"/>
+    <range space="io"/>
+    <range space="pciconf"/>
+  </global>
+  <stackpointer register="SP" space="ram" growth="negative"/>
+  <funcptr align="2"/>
+  <default_proto>
+    <prototype name="fcc911" extrapop="0" stackshift="0" strategy="register">
+      <input killedbycall="false">
+        <pentry minsize="1" maxsize="4">
+          <register name="ACC"/>
+        </pentry>
+      </input>
+      <output>
+        <pentry minsize="1" maxsize="4">
+          <register name="ACC"/>
+        </pentry>
+      </output>
+    </prototype>
+  </default_proto>
+</compiler_spec>

data/languages/xcodelatedbug.ldefs

@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/language_definitions.rxg -->
+
+<language_definitions>
+<!-- Uncomment the following to make the language available in Ghidra -->
+   <language processor="mcpxcode"
+            endian="little"
+            size="32"
+            variant="LATEDBUG"
+            version="1.0"
+            slafile="xcodelatedbug.sla"
+            processorspec="xcodelatedbug.pspec"
+            id="mcpxcode:LE:32:LATEDBUG">
+    <description>Skeleton Language Module</description>
+    <compiler name="default" spec="xcodelatedbug.cspec" id="default"/>
+  </language> 
+</language_definitions>

data/languages/xcodelatedbug.opinion

@@ -0,0 +1,12 @@
+<opinions>
+<!-- Example of importer opinions - commented-out to prevent use by Ghidra -->
+<!-- The primary and secondary constraint values must be specifide as a decimal string -->
+<!--
+    <constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
+    		<constraint primary="40"   secondary="123"  processor="Skel"  size="16" variant="default" />
+    </constraint>
+    <constraint loader="MS Common Object File Format (COFF)" compilerSpecID="default">
+        <constraint primary="61"                    processor="Skel"  size="16" variant="default" />
+    </constraint>
+-->
+</opinions>

data/languages/xcodelatedbug.pspec

@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/processor_spec.rxg -->
+
+<processor_spec>
+  <programcounter register="PC"/>
+</processor_spec>

data/languages/xcodelatedbug.sinc

@@ -0,0 +1,130 @@
+# sleigh include file for MCPX Code language instructions
+
+define token instr (40)
+	op8 = (0,7)
+
+	cop8 = (8,15)
+
+	u32a = (8,39)
+;
+
+define token instrb (32)
+	u32b = (0, 31)
+;
+
+define pcodeop unk_op;
+define pcodeop exit;
+
+REL: reloc is u32b [ reloc = inst_next + u32b; ] {
+	export *:4 reloc;
+}
+
+CREL: reloc is epsilon [ reloc = inst_next + ACC; ] {
+	export *:4 reloc;
+}
+
+# PCI Config add to memory addr
+# 0x80000000 | bus << 16 | device << 11 | function <<  8 | offset
+#
+# mask = 0x80000880 ^ 0x80000000
+#
+# bus = (mask > 16) & 0xFF
+# device = (mask > 11) & 0x1F
+# func = (mask > 8) & 0x7
+# reg = mask & 0xFF
+#
+# target = bus << 24 | device << 16 | function << 8 | reg
+
+PCI: conf is u32a [ 
+	conf = (((u32a >> 16) & 0xFF) << 24) | (((u32a >> 11) & 0x1F) << 16) | (((u32a >> 8) & 0x7) << 8) | (u32a & 0xFF);	
+] {
+	export *[pciconf]:4 conf;
+}
+################################################################
+
+:xc_mem_read u32a is op8=0x09 & u32a ; u32b {
+	ACC = *[ram]:4 u32a:4;
+}
+
+:xc_mem_write u32a, u32b is op8=0x03 & u32a ; u32b {
+	*[ram]:4 u32a:4 = u32b:4;
+}
+
+:xc_pci_write PCI, u32b is op8=0x01 & PCI ; u32b {
+	PCI = u32b:4;
+}
+
+:xc_pci_read PCI is op8=0x05 & PCI ; u32b {
+	ACC = PCI;
+}
+
+:xc_andor u32a, u32b is op8=0x06 & u32a ; u32b {
+	ACC = ACC & u32a:4;
+	ACC = ACC | u32b:4;
+}
+
+:xc_jne u32a, REL is op8=0x04 & u32a ; REL {
+	if ACC == u32a:4 goto REL;
+}
+
+:xc_jmp REL is op8=0x07 ; REL {
+	goto REL;
+}
+
+:xc_io_write u32a, u32b is op8=0x02 & u32a ; u32b {
+	*[io]:1 u32a:2 = u32b:1;
+}
+
+:xc_io_read u32a is op8=0x08 & u32a ; u32b {
+	ACC = zext(*[io]:1 u32a:2);
+} 
+
+:xc_exit is op8=0xEE {
+	exit();
+	goto inst_start;
+}
+
+:xc_chain ^"xc_mem_read", u32b is op8=0xE1 & cop8=0x09 ; u32b {
+	ACC = *:4 u32b:4;
+}
+
+:xc_chain ^"xc_mem_write", u32b is op8=0xE1 & cop8=0x03 ; u32b {
+	*:4 u32b:4 = ACC:4;
+}
+
+:xc_chain ^"xc_pci_write", u32b is op8=0xE1 & cop8=0x01 ; u32b {
+	*[pciconf]:4 u32b:4 = ACC:4;
+}
+
+:xc_chain ^"xc_pci_read", u32b is op8=0xE1 & cop8=0x05 ; u32b {
+	ACC = *[pciconf]:4 u32b:4;
+}
+
+:xc_chain ^"xc_andor", u32b is op8=0xE1 & cop8=0x06 ; u32b {
+	ACC = ACC & u32b:4;
+	ACC = ACC | ACC;
+}
+
+:xc_chain ^"xc_jne", u32b, CREL is op8=0xE1 & cop8=0x04 ; u32b & CREL {
+	if ACC == u32b:4 goto CREL;
+}
+
+:xc_chain ^"xc_jmp", CREL is op8=0xE1 & cop8=0x07 ; u32b & CREL {
+	goto CREL;
+}
+
+:xc_chain ^"xc_io_write", u32b is op8=0xE1 & cop8=0x02 ; u32b {
+	*[io]:1 u32b:2 = ACC:1;
+}
+
+:xc_chain ^"xc_io_read", u32b is op8=0xE1 & cop8=0x08 ; u32b {
+	ACC = zext(*[io]:1 u32b:2);
+}
+
+:xc_chain ^"xc_unk_"^cop8, u32b is op8=0xE1 & cop8; u32b {
+	unk_op(cop8:1, u32b:4, ACC:4);
+}
+
+:xc_unk_^op8 u32a, u32b is op8 & u32a ; u32b {
+	unk_op(op8:1, u32a:4, u32b:4);
+}

data/languages/xcodelatedbug.slaspec

@@ -0,0 +1,17 @@
+# sleigh specification file for Skeleton Processor
+#   >> see docs/languages/sleigh.htm or sleigh.pdf for Sleigh syntax
+# Other language modules (see Ghidra/Processors) may provide better examples
+# when creating a new language module.
+
+define endian=little;
+define alignment=1;
+
+define space ram     type=ram_space      size=4  default;
+define space io      type=ram_space      size=2;
+define space pciconf type=ram_space		 size=4;
+
+define space register type=register_space size=1;
+
+define register offset=0x00 size=4 [ PC ACC ACC2 SP ];
+
+@include "xcodedbug.sinc"