Byt soft lockup fixes

payloads/external/Makefile.mk

@@ -169,12 +169,13 @@ IPXE_EFI := payloads/external/iPXE/ipxe/ipxe.rom
 endif
 
 $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) $(IPXE_EFI)
-	$(MAKE) -C payloads/external/edk2 DasharoPayloadPkg \
+	$(MAKE) -C payloads/external/edk2 \
 		HOSTCC="$(HOSTCC)" \
 		CC="$(HOSTCC)" \
 		CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \
 		CONFIG_EDK2_TAG_OR_REV=$(CONFIG_EDK2_TAG_OR_REV) \
 		CONFIG_EDK2_UEFIPAYLOAD=$(CONFIG_EDK2_UEFIPAYLOAD) \
+		CONFIG_EDK2_DASHAROPAYLOAD=$(CONFIG_EDK2_DASHAROPAYLOAD) \
 		CONFIG_EDK2_UNIVERSAL_PAYLOAD=$(CONFIG_EDK2_UNIVERSAL_PAYLOAD) \
 		CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \
 		CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \

payloads/external/edk2/Kconfig

@@ -4,14 +4,14 @@ if PAYLOAD_EDK2
 
 config PAYLOAD_FILE
 	string "edk2 binary"
-	default "$(obj)/UEFIPAYLOAD.fd" if EDK2_UEFIPAYLOAD
+	default "$(obj)/UEFIPAYLOAD.fd" if EDK2_UEFIPAYLOAD || EDK2_DASHAROPAYLOAD
 	default "$(obj)/ShimmedUniversalPayload.elf" if EDK2_UNIVERSAL_PAYLOAD
 	help
 	  The result of a UefiPayloadPkg build
 
 choice
 	prompt "EDK II build type"
-	default EDK2_UEFIPAYLOAD
+	default EDK2_DASHAROPAYLOAD
 	help
 	  Select the build type for edk2. UniversalPayload is recommended, as it is
 	  replacing UefiPayloadPkg. Whilst in the transition phase between the two,
@@ -22,6 +22,11 @@ config EDK2_UEFIPAYLOAD
 	help
 	  Build the standard UefiPayloadPkg
 
+config EDK2_DASHAROPAYLOAD
+	bool "Build DasharoPayloadPkg"
+	help
+	  Build the DasharoPayloadPkg
+
 config EDK2_UNIVERSAL_PAYLOAD
 	bool "Build Universal Payload"
 	help

payloads/external/edk2/Makefile

@@ -26,11 +26,16 @@ endif
 
 OBJCOPY = $(GCC_PREFIX)objcopy
 
+ifeq ($(CONFIG_EDK2_DASHAROPAYLOAD),y)
 PAYLOAD_NAME=DasharoPayloadPkg
+BUILD_STR += -p $(PAYLOAD_NAME)/$(PAYLOAD_NAME).dsc
+endif
 
 ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y)
+PAYLOAD_NAME=UefiPayloadPkg
 BUILD_STR += -p $(PAYLOAD_NAME)/$(PAYLOAD_NAME).dsc
 endif
+
 BUILD_STR += -t COREBOOT
 BUILD_STR += -D BOOTLOADER=COREBOOT
 ifneq ($(V),1)

src/lib/reg_script.c

@@ -268,7 +268,7 @@ static uint32_t reg_script_read_iosf(struct reg_script_context *ctx)
 		return iosf_port55_read(step->reg);
 	case IOSF_PORT_0x58:
 		return iosf_port58_read(step->reg);
-	case IOSF_PORT_0x59:
+	case IOSF_PORT_OTG:
 		return iosf_port59_read(step->reg);
 	case IOSF_PORT_0x5a:
 		return iosf_port5a_read(step->reg);
@@ -336,7 +336,7 @@ static void reg_script_write_iosf(struct reg_script_context *ctx)
 	case IOSF_PORT_0x58:
 		iosf_port58_write(step->reg, step->value);
 		break;
-	case IOSF_PORT_0x59:
+	case IOSF_PORT_OTG:
 		iosf_port59_write(step->reg, step->value);
 		break;
 	case IOSF_PORT_0x5a:

src/mainboard/intel/minnowmax/acpi/mainboard.asl

@@ -17,3 +17,13 @@ Scope (\_SB) {
 		Name(_HID, EisaId("PNP0C0C"))
 	}
 }
+
+Scope(\_GPE)
+{
+	/* PMC_WAKE_PCIE0 connected to LAN on RP3 */
+	Method (_L03)
+	{
+		PWS0 = 1
+		Notify (\_SB.PCI0.RP03, 0x02)
+	}
+}

src/mainboard/intel/minnowmax/devicetree.cb

@@ -29,15 +29,13 @@ chip soc/intel/baytrail
 	register "sdcard_cap_low" = "0x076864b2"
 	register "sdcard_cap_high" = "0x0"
 
-	# VR PS2 control
-	register "vnn_ps2_enable" = "1"
-	register "vcc_ps2_enable" = "1"
-
 	# Allow PCIe devices to wake system from suspend
 	register "pcie_wake_enable" = "1"
 
+	register "lpe_acpi_mode" = "1"
 	register "lpss_acpi_mode" = "1"
 	register "scc_acpi_mode" = "1"
+	register "otg_acpi_mode" = "1"
 
 	# Disable SLP_X stretching after SUS power well fail.
 	register "disable_slp_x_stretch_sus_fail" = "1"

src/soc/intel/baytrail/Makefile.mk

@@ -41,6 +41,7 @@ ramstage-y += lpe.c
 ramstage-y += lpss.c
 ramstage-y += memmap.c
 ramstage-y += northcluster.c
+ramstage-y += otg.c
 ramstage-y += pcie.c
 ramstage-y += perf_power.c
 ramstage-y += pmutil.c

src/soc/intel/baytrail/acpi.c

@@ -156,8 +156,12 @@ static void generate_p_state_entries(int core)
 	vid_max = pattrs->iacore_vids[IACORE_MAX];
 	vid_min = pattrs->iacore_vids[IACORE_LFM];
 
-	/* Set P-states coordination type based on MSR disable bit */
-	coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL;
+	/*
+	 * Set P-states coordination type based on MSR disable bit.
+	 * We disable SINGLE_PCTL and INDP_AUTOCM in core_msr_script,
+	 * so we can only use HW_ALL(using MIN_CLIP) per BWG.
+	 */
+	coord_type = HW_ALL;
 
 	/* Max Non-Turbo Frequency */
 	clock_max = (ratio_max * pattrs->bclk_khz) / 1000;
@@ -175,7 +179,7 @@ static void generate_p_state_entries(int core)
 	acpigen_write_PPC_NVS();
 
 	/* Write PSD indicating configured coordination type */
-	acpigen_write_PSD_package(core, 1, coord_type);
+	acpigen_write_PSD_package(0, pattrs->num_cpus, coord_type);
 
 	/* Add P-state entries in _PSS table */
 	acpigen_write_name("_PSS");

src/soc/intel/baytrail/acpi/device_nvs.asl

@@ -22,6 +22,7 @@ Field (DNVS, ByteAcc, NoLock, Preserve)
 	C1EN,	8,	/* SDIO Enable */
 	C2EN,	8,	/* SD Card Enable */
 	LPEN,	8,	/* LPE Enable */
+	UOEN,	8,	/* USB OTG Enable */
 
 	/* BAR 0 */
 
@@ -43,6 +44,7 @@ Field (DNVS, ByteAcc, NoLock, Preserve)
 	C1B0,	32,	/* SDIO BAR0 */
 	C2B0,	32,	/* SD Card BAR0 */
 	LPB0,	32,	/* LPE BAR0 */
+	UOB0,	32,	/* USB OTG BAR0 */
 
 	/* BAR 1 */
 
@@ -64,6 +66,7 @@ Field (DNVS, ByteAcc, NoLock, Preserve)
 	C1B1,	32,	/* SDIO BAR1 */
 	C2B1,	32,	/* SD Card BAR1 */
 	LPB1,	32,	/* LPE BAR1 */
+	UOB1,	32,	/* USB OTG BAR1 */
 
 	/* Extra */
 

src/soc/intel/baytrail/acpi/gpio.asl

@@ -95,3 +95,80 @@ Device (GPSS)
 		Return (0xF)
 	}
 }
+
+Device (GPED)
+{
+	Name (_HID, "INT0002")
+	Name (_CID, "INT0002")
+	Name (_DDN, "Virtual GPIO controller")
+	Name (_UID, 1)
+
+	Name (RBUF, ResourceTemplate ()
+	{
+		Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 9 }
+	})
+
+	Method (_CRS, 0, Serialized)
+	{
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0)
+	}
+
+	Name (GBUF, ResourceTemplate ()
+	{
+		GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullDown, 0x0000,
+			"\\_SB.GPED", 0x00, ResourceConsumer,,) { 2 }
+	})
+
+	Method (_AEI, 0, Serialized)
+	{
+		Return (GBUF)
+	}
+
+	Method (_E02, 0, NotSerialized)
+	{
+		If (PWBS)
+		{
+			PWBS = 1
+		}
+
+		If (PMEB)
+		{
+			PMEB = 1
+		}
+
+		If (\_SB.PCI0.SATA.PMES)
+		{
+			\_SB.PCI0.SATA.PMES = 1
+			Notify (\_SB.PCI0.SATA, 0x02)
+		}
+
+		If (\_SB.PCI0.EM45.PMES && (\C0EN == 0))
+		{
+			\_SB.PCI0.EM45.PMES = 1
+			Notify (\_SB.PCI0.EM45, 0x02)
+		}
+
+		If (\_SB.PCI0.HDA.PMES)
+		{
+			\_SB.PCI0.HDA.PMES = 1
+			Notify (\_SB.PCI0.HDA, 0x02)
+		}
+
+		If (\_SB.PCI0.XHCI.PMES)
+		{
+			\_SB.PCI0.XHCI.PMES = 1
+			Notify (\_SB.PCI0.XHCI, 0x02)
+		}
+
+		If (\_SB.PCI0.SEC0.PMES == 1)
+		{
+			\_SB.PCI0.SEC0.PMES |= 0
+			Notify (\_SB.PCI0.SEC0, 0x02)
+		}
+	}
+}

src/soc/intel/baytrail/acpi/hda.asl

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(HDA)
+{
+	Name(_ADR,0x001b0000)
+
+	OperationRegion (PMEB, PCI_Config, 0x74, 0x04)
+	Field (PMEB, WordAcc, NoLock, Preserve)
+	{
+		,	8,
+		PMEE,	1,
+		,	6,
+		PMES,	1
+	}
+}

src/soc/intel/baytrail/acpi/lpc.asl

@@ -44,7 +44,6 @@ Device (LPCB)
 		})
 	}
 
-#if !CONFIG(DISABLE_HPET)
 	Device (HPET)
 	{
 		Name (_HID, EISAID("PNP0103"))
@@ -60,7 +59,6 @@ Device (LPCB)
 			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400)
 		})
 	}
-#endif
 
 	Device(PIC)	/* 8259 Interrupt Controller */
 	{
@@ -130,6 +128,16 @@ Device (LPCB)
 		})
 	}
 
+	Device (FPU)	/* x87-compatible Floating Point Processing Unit */
+	{
+		Name (_HID, EisaId ("PNP0C04"))
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x01)
+			IRQNoFlags () {13}
+		})
+	}
+
 #if CONFIG(ENABLE_BUILTIN_COM1)
 	Device (COM1) {
 		Name (_HID, EISAID ("PNP0501"))

src/soc/intel/baytrail/acpi/otg.asl

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (OTG)
+{
+	Name (_HID, "80860F37")
+	Name (_CID, "80860F37")
+	Name (_UID, 1)
+	Name (_DDN, "USB OTG Controller")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0)
+		Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1)
+	})
+
+	Method (_CRS)
+	{
+		/* Update BAR0 from NVS */
+		CreateDwordField (^RBUF, ^BAR0._BAS, BAS0)
+		BAS0 = \UOB0
+
+		/* Update BAR1 from NVS */
+		CreateDwordField (^RBUF, ^BAR1._BAS, BAS1)
+		BAS1 = \UOB1
+
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (\UOEN == 1) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+}