mb/msi/ms7d25,7eo6: Fix USB 3.x port mapping

The USB-C port is Gen2x2 and occupies two USB3.x line pairs. The missing second pair caused all the ports to be shifted by one and port 10 not being enabled as USB3.x capable. As a result one of the JUSB3 ports was working in HighSpeed only. Signed-off-by: Michał Żygowski <[email protected]>
Dasharo · Nov 5, 2024 · 6a842ff · 6a842ff
1 parent 26ab7d9
commit 6a842ff
Show file tree

Hide file tree

Showing 2 changed files with 20 additions and 20 deletions.
diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb
@@ -74,16 +74,16 @@ chip soc/intel/alderlake
 			register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1
 			register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2
 
-			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1
-			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1
-			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5
-			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2
-			register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2
-			register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4
-			register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4
-			register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3
-			register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3
-			register "usb3_ports[9]" = "USB3_PORT_EMPTY"
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C Gen2x2 LAN_USB1
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-C Gen2x2 LAN_USB1
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5
+			register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2
+			register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2
+			register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4
+			register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4
+			register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3
+			register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3
 		end
 		device ref cnvi_wifi on
 			# Enable CNVi BT

diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb
@@ -76,16 +76,16 @@ chip soc/intel/alderlake
 			register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1
 			register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2
 
-			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1
-			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1
-			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5
-			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2
-			register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2
-			register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4
-			register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4
-			register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3
-			register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3
-			register "usb3_ports[9]" = "USB3_PORT_EMPTY"
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C Gen2x2 LAN_USB1
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-C Gen2x2 LAN_USB1
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5
+			register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2
+			register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2
+			register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4
+			register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4
+			register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3
+			register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3
 		end
 		device ref cnvi_wifi on
 			# Enable CNVi BT