mb/lenovo/m900_tiny: add board

Add Lenovo ThinkCentre M700 / M900 Tiny mainboard.

The M700 / M900 Tiny boards are USFF PCs that come with Skylake LGA1151
processors. M700 comes with B150 chipset, M900 comes with Q170 and is
vPro capable.

There is an onboard discrete TPM 1.2. Intel PTT fTPM can also be enabled
in vendor FW, but for now it's not used here.

An ME_DIS header (FDOPSS) can be set to disable the ME. This is also
recommended since the ME can get stuck in a disabled state from which
coreboot can't re-enable it, causing a bootloop.

Boots to Fedora 38 w/ kernel 6.5.5 and Windows 11.

Tested and working:

- Serial port (via optional module)
- Rear DisplayPort connectors
- Graphics w/ libgfxinit
- Ethernet
- SATA
- NVMe
- Internal speaker, front combo jack, rear line-out
- Discrete TPM 1.2
- USB ports (Port 1 untested, apparently broken on my unit)
- M.2 2230 Wi-Fi slot (needs ASPM disabled)
- S3 suspend

Untested:

- Front mic input
- Optional expansion headers: DisplayPort, USB, PS/2, SATA / PCIe

Change-Id: I6786e068ec03c8bf243e1767cd7b9d50512ea77f
Signed-off-by: Michał Kopeć <[email protected]>

src/mainboard/lenovo/m900_tiny/Kconfig

@@ -0,0 +1,48 @@
+if BOARD_LENOVO_THINKCENTRE_M900_TINY
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_UART_8250IO
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_INT15
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_HAS_TPM1
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select MEMORY_MAPPED_TPM
+	select SKYLAKE_SOC_PCH_H
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_KABYLAKE
+	select SUPERIO_NUVOTON_NCT6687D
+
+config DISABLE_HECI1_AT_PRE_BOOT
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2 if INTEL_LPSS_UART_FOR_CONSOLE
+	default 0
+
+config MAINBOARD_DIR
+	default "lenovo/m900_tiny"
+
+config MAINBOARD_PART_NUMBER
+	default "ThinkCentre M700 / M900 Tiny"
+
+config PRERAM_CBMEM_CONSOLE_SIZE
+	hex
+	default 0xd00
+
+config DIMM_SPD_SIZE
+	default 512 #DDR4
+
+# TODO: fix and enable
+config DRIVER_LENOVO_SERIALS
+	bool
+	default n
+
+endif

src/mainboard/lenovo/m900_tiny/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_LENOVO_THINKCENTRE_M900_TINY
+	bool "ThinkCentre M700 / M900 Tiny"

src/mainboard/lenovo/m900_tiny/Makefile.inc

@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+subdirs-y += spd
+bootblock-y += bootblock.c
+
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/lenovo/m900_tiny/acpi/ec.asl

@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */

src/mainboard/lenovo/m900_tiny/acpi/superio.asl

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define SUPERIO_DEV		SIO0
+#define SUPERIO_PNP_BASE	0x2e
+#define NCT6687D_SHOW_SP1
+#define NCT6687D_SHOW_EC
+
+#include <superio/nuvoton/nct6687d/acpi/superio.asl>

src/mainboard/lenovo/m900_tiny/board.fmd

@@ -0,0 +1,14 @@
+FLASH@4278190080 0x01000000 {
+	SI_DESC@0x0 0x1000
+	SI_GBE@0x1000 0x2000
+	SI_ME@0x3000 0x7FD000
+	SI_BIOS 16777216 {
+		CONSOLE@0 0x20000
+		RW_MRC_CACHE@131072 0x10000
+		SMMSTORE@196608 0x40000
+
+
+		FMAP@458752 0x200
+		COREBOOT(CBFS)@459264 16317952
+	}
+}

src/mainboard/lenovo/m900_tiny/board_info.txt

@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://psref.lenovo.com/Product/ThinkCentre_M900_Tiny
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2015

src/mainboard/lenovo/m900_tiny/bootblock.c

@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <soc/gpio.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6687d/nct6687d.h>
+#include "include/gpio.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6687D_SP1)
+#define POWER_DEV PNP_DEV(0x2e, NCT6687D_SLEEP_PWR)
+
+static void early_config_gpio(void)
+{
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+		gpio_configure_pads(uart_gpio_table, ARRAY_SIZE(uart_gpio_table));
+}
+
+void bootblock_mainboard_init(void)
+{
+	early_config_gpio();
+}
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Replicate vendor settings for multi-function pins in global config LDN */
+	nuvoton_pnp_enter_conf_state(SERIAL_DEV);
+	pnp_write_config(SERIAL_DEV, 0x13, 0x0c);
+
+	/* Below are multi-pin function */
+	pnp_write_config(SERIAL_DEV, 0x1d, 0x08);
+	pnp_write_config(SERIAL_DEV, 0x1f, 0xf0);
+	pnp_write_config(SERIAL_DEV, 0x22, 0xbc);
+	pnp_write_config(SERIAL_DEV, 0x23, 0xdf);
+	pnp_write_config(SERIAL_DEV, 0x24, 0x81);
+	pnp_write_config(SERIAL_DEV, 0x25, 0xff);
+	pnp_write_config(SERIAL_DEV, 0x29, 0x6d);
+	pnp_write_config(SERIAL_DEV, 0x2a, 0x8f);
+
+	pnp_set_logical_device(POWER_DEV);
+	/* Configure pin for PECI */
+	pnp_write_config(POWER_DEV, 0xf3, 0x0c);
+
+	nuvoton_pnp_exit_conf_state(POWER_DEV);
+
+	/* Enable serial only if COM1 header is populated */
+	if (CONFIG(CONSOLE_SERIAL) && !gpio_get(GPP_A22))
+		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}

src/mainboard/lenovo/m900_tiny/cmos.default

@@ -0,0 +1,4 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable

src/mainboard/lenovo/m900_tiny/cmos.layout

@@ -0,0 +1,60 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID	name
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	6	debug_level
+
+# coreboot config options: cpu
+400	1	e	2	hyper_threading
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+409	2	e	7	power_on_after_fail
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416	128	r	0	vbnv
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+2	0	Disable
+2	1	Enable
+4	0	Fallback
+4	1	Normal
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+7	0	Disable
+7	1	Enable
+7	2	Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984