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1. Multi-core-Paillier-Acceleration-System Multi-core-Paillier-Acceleration-System Public

   This work presents the RTL design of a multi-core Paillier acceleration system. It supports four types of acceleration: Paillier encryption, Paillier decryption, homomorphic addition, and homomorph…

   SystemVerilog 5 1

2. AVS3-RDOQ AVS3-RDOQ Public

   This work presents the RTL design from our paper published in the journal TCSVT: 'Parallelized RDOQ Algorithm and Fully Pipelined Hardware Architecture for AVS3 Video Coding.'

   SystemVerilog 1

3. Video-Stitching Video-Stitching Public

   This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface. The interface can be easily switched to the DDR3/4 located …

   Verilog 9 1

4. AXIS-AXI4-AXIS AXIS-AXI4-AXIS Public

   This project is designed to delay the output of the video stream in AXI-STREAM format.

   Verilog 9 3

5. Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm Public

   The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boa…

   Verilog 28 3

6. Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm Public

   The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPG…

   Verilog 32