IC Design and Verification | Electronics Engineer
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Rydev
- Costa Rica
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08:17
(UTC -06:00) - @DavidMedinaMay1
Highlights
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gray_decoder-FPGAOL_CAAS_test
gray_decoder-FPGAOL_CAAS_test PublicAcademic project to test the https://caas.symbioticeda.com/ platform.
Verilog 1
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open_source_fpga_environment
open_source_fpga_environment Publicopen source toolchain for developing fpga projects
SystemVerilog
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Quine-McCluskey-LD
Quine-McCluskey-LD PublicImplementación de algoritmos relacionados a la minimización de ecuaciones booleanas.
Jupyter Notebook
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inversor_minimo_XT018
inversor_minimo_XT018 PublicTarea_1_Introducción al diseño de circuitos integrados
Python
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