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RC 1.4.11 (aws#464)
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Release 1.4.11

* FPGA developer kit now supports Xilinx SDx/Vivado 2019.1
    * To upgrade, use Developer AMI v1.7.0 on the AWS Marketplace. The Developer Kit scripts (hdk_setup.sh or sdaccel_setup.sh) will detect the tool version and update the environment based on requirements needed for Xilinx 2019.1 tools.
* New functionality:
    * Added a developer resources section that provides guides on how to setup your own GUI Desktop and compute cluster environment.
    * Developers can now ask for AFI limit increases via the AWS Support Center Console
        * Create a case to increase your `EC2 FPGA` service limit from the console.
    * HLx IPI flow updates
        * HLx support for AXI Fast Memory mode.
        * HLx support for 3rd party simulations.
        * HLx support for changes in shell and AWS IP updates(e.g. sh_ddr).
* Bug Fixes:
    * Documentation fixes in the Shell Interface Specification
* Fixes for forum questions
        * Unable to compile aws_v1_0_vl_rfs.sv in Synopsys VCS
        * Use fpga_mgmt init in HLx runtime
    * New XRT versions added to the XRT Installation Instructions to fix segmentation faults when using xclbin instead of awsxclbin files.
* Deprecations:
    * Removed GUI Setup scripts from AMI v1.7.0 onwards.
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@deeppat
deeppat authored Sep 20, 2019
1 parent 2fa6b06 commit 099d489
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3 changes: 3 additions & 0 deletions .gitmodules
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Expand Up @@ -10,3 +10,6 @@
path = SDAccel/examples/xilinx_2018.3
url = https://github.com/Xilinx/SDAccel_Examples.git
branch = master
[submodule "SDAccel/examples/xilinx_2019.1"]
path = SDAccel/examples/xilinx_2019.1
url = https://github.com/Xilinx/SDAccel_Examples.git
9 changes: 9 additions & 0 deletions ERRATA.md
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Expand Up @@ -9,6 +9,15 @@
* DRAM Data retention is not supported for CL designs with less than 4 DDRs enabled
* Combinatorial loops in CL designs are not supported.

### 2019.1
* Vivado `compile_simlib` command fails to generate the following verilog IP libraries for the following simulators.

| Library(verilog) | Simulator |
|---|---|
| `sync_ip` | Cadence IES |
| `hdmi_gt_controller_v1_0_0` | Synopsys VCS |
* We are working with Xilinx to provide a fix for these.

## SDK

## SDAccel (For additional restrictions see [SDAccel ERRATA](./SDAccel/ERRATA.md))
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119 changes: 76 additions & 43 deletions FAQs.md
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140 changes: 81 additions & 59 deletions Jenkinsfile
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Expand Up @@ -122,15 +122,16 @@ task_label = [
]

// Put the latest version last
def xilinx_versions = [ '2017.4', '2018.2', '2018.3' ]
def xilinx_versions = [ '2017.4', '2018.2', '2018.3', '2019.1' ]

// We want the default to be the latest.
def default_xilinx_version = xilinx_versions.last()

def dsa_map = [
'2017.4' : [ 'DYNAMIC_5_0' : 'dyn'],
'2018.2' : [ 'DYNAMIC_5_0' : 'dyn'],
'2018.3' : [ 'DYNAMIC_5_0' : 'dyn']
'2018.3' : [ 'DYNAMIC_5_0' : 'dyn'],
'2019.1' : [ 'DYNAMIC_5_0' : 'dyn']
]

def sdaccel_example_default_map = [
Expand All @@ -153,6 +154,12 @@ def sdaccel_example_default_map = [
'Gmem_2Banks_2ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/gmem_2banks_ocl',
'Kernel_Global_Bw_4ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/kernel_global_bandwidth',
'RTL_Vadd_Debug': 'SDAccel/examples/xilinx/getting_started/rtl_kernel/rtl_vadd_hw_debug'
],
'2019.1' : [
'Hello_World_1ddr': 'SDAccel/examples/xilinx/getting_started/hello_world/helloworld_ocl',
'Gmem_2Banks_2ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/gmem_2banks_ocl_5.0_shell',
'Kernel_Global_Bw_4ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/kernel_global_bandwidth_5.0_shell',
'RTL_Vadd_Debug': 'SDAccel/examples/xilinx/getting_started/rtl_kernel/rtl_vadd_hw_debug'
]
]

Expand All @@ -174,6 +181,12 @@ def simulator_tool_default_map = [
'vcs': 'synopsys/vcs-mx/N-2017.12-SP2',
'questa': 'questa/10.6c_1',
'ies': 'incisive/15.20.063'
],
'2019.1' : [
'vivado': 'xilinx/SDx/2019.1.op2552052',
'vcs': 'synopsys/vcs-mx/N-2017.12-SP2',
'questa': 'questa/10.6c_1',
'ies': 'incisive/15.20.063'
]
]

Expand Down Expand Up @@ -270,7 +283,7 @@ def test_run_py_bindings() {
try {
sh """
set -e
source $WORKSPACE/shared/tests/bin/setup_test_sdk_env_al2.sh "py_bindings"
source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh "py_bindings"
python2.7 -m pytest -v $WORKSPACE/${test} --junit-xml $WORKSPACE/${report_file}
"""
} catch (exc) {
Expand Down Expand Up @@ -368,7 +381,7 @@ def test_fpga_all_slots() {
}
catch (exception) {
echo "Test FPGA Tools All Slots failed"
input message: "1 slot FPGA Tools test failed. Click Proceed or Abort when you are done debugging on the instance."
input message: "All slot FPGA Tools test failed. Click Proceed or Abort when you are done debugging on the instance."
throw exception
}
finally {
Expand Down Expand Up @@ -396,7 +409,6 @@ def test_run_non_root_access() {
source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh
newgrp fpgauser
export SDK_DIR="${WORKSPACE}/sdk"
source $WORKSPACE/shared/tests/bin/setup_test_env.sh
python2.7 -m pytest -v $WORKSPACE/${test} --junit-xml $WORKSPACE/${report_file}
"""
} catch (exc) {
Expand Down Expand Up @@ -599,15 +611,15 @@ if (test_xdma) {
//=============================================================================
// Python Binding Test
//=============================================================================
if (test_py_bindings) {
all_tests['Test Python Bindings'] = {
stage('Test Python Bindings') {
node('f1.2xl_runtime_test_al2') {
test_run_py_bindings()
}
}
}
}
// if (test_py_bindings) {
// all_tests['Test Python Bindings'] = {
// stage('Test Python Bindings') {
// node('f1.2xl_runtime_test_al2') {
// test_run_py_bindings()
// }
// }
// }
// }

//=============================================================================
// Precompiled Runtime Tests
Expand Down Expand Up @@ -873,34 +885,34 @@ if (test_hdk_fdf) {
// SDAccel Tests
//=============================================================================

if (test_sdaccel_scripts) {
all_tests['Test SDAccel Scripts'] = {
stage('Test SDAccel Scripts') {
def nodes = [:]
for (def xilinx_version in xilinx_versions) {

String node_label = get_task_label(task: 'source_scripts', xilinx_version: xilinx_version)
String node_name = "Test SDAccel Scripts ${xilinx_version}"
nodes[node_name] = {
node(node_label) {
String report_file = "test_sdaccel_scripts_${xilinx_version}.xml"
checkout scm
try {
sh """
set -e
source $WORKSPACE/shared/tests/bin/setup_test_env.sh
python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_sdaccel_scripts.py --junit-xml $WORKSPACE/${report_file}
"""
} finally {
run_junit(report_file)
}
}
}
}
parallel nodes
}
}
}
// if (test_sdaccel_scripts) {
// all_tests['Test SDAccel Scripts'] = {
// stage('Test SDAccel Scripts') {
// def nodes = [:]
// for (def xilinx_version in xilinx_versions) {
//
// String node_label = get_task_label(task: 'source_scripts', xilinx_version: xilinx_version)
// String node_name = "Test SDAccel Scripts ${xilinx_version}"
// nodes[node_name] = {
// node(node_label) {
// String report_file = "test_sdaccel_scripts_${xilinx_version}.xml"
// checkout scm
// try {
// sh """
// set -e
// source $WORKSPACE/shared/tests/bin/setup_test_env.sh
// python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_sdaccel_scripts.py --junit-xml $WORKSPACE/${report_file}
// """
// } finally {
// run_junit(report_file)
// }
// }
// }
// }
// parallel nodes
// }
// }
// }

if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
all_tests['Run SDAccel Tests'] = {
Expand Down Expand Up @@ -995,6 +1007,7 @@ if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
}

boolean test_sw_emu_supported = true
boolean test_hw_emu_supported = true

if(description_json["targets"]) {
if(description_json["targets"].contains("sw_emu")) {
Expand All @@ -1004,6 +1017,13 @@ if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
test_sw_emu_supported = false
echo "Description file ${description_file} does not have target sw_emu"
}
if(description_json["targets"].contains("hw_emu")) {
test_hw_emu_supported = true
echo "Description file ${description_file} has target sw_emu"
} else {
test_hw_emu_supported = false
echo "Description file ${description_file} does not have target sw_emu"
}
} else {
echo "Description json did not have a 'target' key"
}
Expand Down Expand Up @@ -1032,23 +1052,25 @@ if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
}
}

stage(hw_emu_stage_name) {
node(get_task_label(task: 'sdaccel_builds', xilinx_version: xilinx_version)) {
checkout scm
try {
sh """
set -e
source $WORKSPACE/shared/tests/bin/setup_test_build_sdaccel_env.sh
export AWS_PLATFORM=\$AWS_PLATFORM_${dsa_name}
python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_build_sdaccel_example.py::TestBuildSDAccelExample::test_hw_emu --examplePath ${example_path} --junit-xml $WORKSPACE/${hw_emu_report_file} --timeout=21600 --rteName ${dsa_rte_name} --xilinxVersion ${xilinx_version}
"""
} catch (error) {
echo "${hw_emu_stage_name} HW EMU Build generation failed"
archiveArtifacts artifacts: "${example_path}/**", fingerprint: true
throw error
} finally {
run_junit(hw_emu_report_file)
git_cleanup()
if(test_hw_emu_supported) {
stage(hw_emu_stage_name) {
node(get_task_label(task: 'sdaccel_builds', xilinx_version: xilinx_version)) {
checkout scm
try {
sh """
set -e
source $WORKSPACE/shared/tests/bin/setup_test_build_sdaccel_env.sh
export AWS_PLATFORM=\$AWS_PLATFORM_${dsa_name}
python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_build_sdaccel_example.py::TestBuildSDAccelExample::test_hw_emu --examplePath ${example_path} --junit-xml $WORKSPACE/${hw_emu_report_file} --timeout=21600 --rteName ${dsa_rte_name} --xilinxVersion ${xilinx_version}
"""
} catch (error) {
echo "${hw_emu_stage_name} HW EMU Build generation failed"
archiveArtifacts artifacts: "${example_path}/**", fingerprint: true
throw error
} finally {
run_junit(hw_emu_report_file)
git_cleanup()
}
}
}
}
Expand Down
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