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Load/store as user #54

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Load/store as user #54

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e99117d
Catch up with upstream sail-riscv
nwf-msr Oct 22, 2021
72454e9
Add a fast-cap-dirty PTE behavior
nwf-msr Nov 12, 2020
a356e24
Refactor checkPTEPermission
nwf-msr Nov 12, 2020
3b7bcfe
Prepare xccsr for s-mode bits
nwf-msr Dec 3, 2020
b002cd5
Introduce load-capability generation traps
nwf-msr Nov 12, 2020
3e007ae
Split handle_load_cap_via_cap into worker/wrapper
nwf-msr Sep 29, 2021
0c241c6
Split CJALR execution into worker/wrapper
nwf-msr May 6, 2021
69acf10
Indirect sentries, Load-PCC flavor
nwf-msr May 6, 2021
9b0c4c8
Refactorings to prepare for explict cap-auth load/store as-user instr…
nwf-msr Oct 20, 2021
8a61c12
Explict cap-auth load/store as-user instructions
nwf-msr Oct 20, 2021
089f8b5
fixup! Explict cap-auth load/store as-user instructions
nwf-msr Oct 30, 2021
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5 changes: 4 additions & 1 deletion Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,8 @@ SAIL_RV64_VM_SRCS = $(SAIL_RISCV_MODEL_DIR)/riscv_vmem_sv39.sail \

SAIL_VM_SRCS = $(SAIL_CHERI_MODEL_DIR)/cheri_pte.sail $(SAIL_CHERI_MODEL_DIR)/cheri_ptw.sail \
$(SAIL_RISCV_MODEL_DIR)/riscv_vmem_common.sail $(SAIL_RISCV_MODEL_DIR)/riscv_vmem_tlb.sail
SAIL_VM_SRCS += $(SAIL_$(ARCH)_VM_SRCS)
SAIL_VM_SRCS += $(SAIL_$(ARCH)_VM_SRCS) \
$(SAIL_CHERI_MODEL_DIR)/cheri_ptw_late.sail

# Non-instruction sources
PRELUDE = $(SAIL_RISCV_MODEL_DIR)/prelude.sail \
Expand Down Expand Up @@ -98,6 +99,7 @@ SAIL_ARCH_SRCS = $(PRELUDE) \
$(SAIL_RISCV_MODEL_DIR)/riscv_types_common.sail \
$(SAIL_CHERI_MODEL_DIR)/cheri_riscv_types.sail \
$(SAIL_RISCV_MODEL_DIR)/riscv_types.sail \
$(SAIL_CHERI_MODEL_DIR)/cheri_riscv_types_late.sail \
$(SAIL_REGS_SRCS) \
$(SAIL_SYS_SRCS) \
$(SAIL_RISCV_MODEL_DIR)/riscv_platform.sail \
Expand All @@ -111,6 +113,7 @@ SAIL_ARCH_RVFI_SRCS = \
$(SAIL_RISCV_MODEL_DIR)/riscv_types_common.sail \
$(SAIL_CHERI_MODEL_DIR)/cheri_riscv_types.sail \
$(SAIL_RISCV_MODEL_DIR)/riscv_types.sail \
$(SAIL_CHERI_MODEL_DIR)/cheri_riscv_types_late.sail \
$(SAIL_REGS_SRCS) \
$(SAIL_SYS_SRCS) \
$(SAIL_RISCV_MODEL_DIR)/riscv_platform.sail \
Expand Down
2 changes: 1 addition & 1 deletion sail-riscv
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Submodule sail-riscv updated from 60776f to 1c7584
6 changes: 6 additions & 0 deletions src/cheri_addr_checks.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -212,6 +212,12 @@ function ext_handle_data_check_error(err : ext_data_addr_error) -> unit = {
handle_cheri_cap_exception(capEx, regnum)
}

/* Default implementations of these hooks permit all accesses. */
function ext_check_phys_mem_read (access_type, paddr, size, aquire, release, reserved, read_meta) =
Ext_PhysAddr_OK ()

function ext_check_phys_mem_write(write_kind, paddr, size, data, metadata) =
Ext_PhysAddr_OK ()

/* Is XRET from given mode permitted by extension? */
function ext_check_xret_priv (p : Privilege) : Privilege -> bool =
Expand Down
4 changes: 4 additions & 0 deletions src/cheri_cap_common.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -416,6 +416,10 @@ function isCapSealed(cap) = signed(cap.otype) != otype_unsealed
val hasReservedOType : Capability -> bool
function hasReservedOType(cap) = unsigned(cap.otype) > cap_max_otype

function isCapSentryOrIsentry(cap) : Capability -> bool =
let sotype = signed(cap.otype) in
(sotype == otype_sentry) | (sotype == otype_isentry_pcc)

function sealCap(cap, otyp) : (Capability, bits(cap_otype_width)) -> Capability =
{cap with otype=otyp}

Expand Down
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